TY - JOUR
T1 - Low-Power, Adaptive Neuromorphic Systems
T2 - Recent Progress and Future Directions
AU - Basu, Arindam
AU - Acharya, Jyotibdha
AU - Karnik, Tanay
AU - Liu, Huichu
AU - Li, Hai
AU - Seo, Jae Sun
AU - Song, Chang
N1 - Publisher Copyright:
© 2011 IEEE.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2018/3
Y1 - 2018/3
N2 - In this paper, we present a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. In particular, we focus on those systems which can either learn from data in an unsupervised or online supervised manner. We present algorithms and architectures developed specially to support on-chip learning. Emphasis is placed on hardware friendly modifications of standard algorithms, such as backpropagation, as well as novel algorithms, such as structural plasticity, developed specially for low-resolution synapses. We cover works related to both spike-based and more traditional non-spike-based algorithms. This is followed by developments in novel devices, such as floating-gate MOS, memristors, and spintronic devices. CMOS circuit innovations for on-chip learning and CMOS interface circuits for post-CMOS devices, such as memristors, are presented. Common architectures, such as crossbar or island style arrays, are discussed, along with their relative merits and demerits. Finally, we present some possible applications of neuromorphic hardware, such as brain-machine interfaces, robotics, etc., and identify future research trends in the field.
AB - In this paper, we present a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. In particular, we focus on those systems which can either learn from data in an unsupervised or online supervised manner. We present algorithms and architectures developed specially to support on-chip learning. Emphasis is placed on hardware friendly modifications of standard algorithms, such as backpropagation, as well as novel algorithms, such as structural plasticity, developed specially for low-resolution synapses. We cover works related to both spike-based and more traditional non-spike-based algorithms. This is followed by developments in novel devices, such as floating-gate MOS, memristors, and spintronic devices. CMOS circuit innovations for on-chip learning and CMOS interface circuits for post-CMOS devices, such as memristors, are presented. Common architectures, such as crossbar or island style arrays, are discussed, along with their relative merits and demerits. Finally, we present some possible applications of neuromorphic hardware, such as brain-machine interfaces, robotics, etc., and identify future research trends in the field.
KW - MOS integrated circuits
KW - Neuromorphics
KW - adaptive systems
KW - artificial neural networks
KW - learning systems
KW - low-power electronics
KW - machine learning
KW - neural network hardware
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U2 - 10.1109/JETCAS.2018.2816339
DO - 10.1109/JETCAS.2018.2816339
M3 - Review article
AN - SCOPUS:85043757783
VL - 8
SP - 6
EP - 27
JO - IEEE Journal on Emerging and Selected Topics in Circuits and Systems
JF - IEEE Journal on Emerging and Selected Topics in Circuits and Systems
SN - 2156-3357
IS - 1
ER -