Low ON-resistance and high current GaN Vertical Electron Transistors with buried p-GaN layers

Ramya Yeluri, Jing Lu, David Browne, Christophe A. Hurni, Srabanti Chowdhury, Stacia Keller, James S. Speck, Umesh K. Mishra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Current Aperture Vertical Electron Transistors (CAVETs) benefit from the high electron mobility of the 2-dimensional electron gas (2-DEG) in the lateral direction and the better field distribution of the vertical geometry. Current flows laterally in the 2-DEG at the AlGaN/GaN heterojunction and is directed vertically down to the drain, through the aperture (Fig.1). A current blocking layer (CBL) is used to define the low resistance aperture. In this work, we use conductive Mg-doped MOCVD p-GaN as the CBL, hence blocking the current flow by the use of a reverse biased p-n junction as opposed to using insulating layers[1,2].

Original languageEnglish (US)
Title of host publicationDevice Research Conference - Conference Digest, DRC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages253-254
Number of pages2
ISBN (Print)9781479954056
DOIs
StatePublished - 2014
Event72nd Device Research Conference, DRC 2014 - Santa Barbara, CA, United States
Duration: Jun 22 2014Jun 25 2014

Other

Other72nd Device Research Conference, DRC 2014
CountryUnited States
CitySanta Barbara, CA
Period6/22/146/25/14

Fingerprint

Electron gas
Transistors
Electrons
Electron mobility
Metallorganic chemical vapor deposition
Heterojunctions
Geometry

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yeluri, R., Lu, J., Browne, D., Hurni, C. A., Chowdhury, S., Keller, S., ... Mishra, U. K. (2014). Low ON-resistance and high current GaN Vertical Electron Transistors with buried p-GaN layers. In Device Research Conference - Conference Digest, DRC (pp. 253-254). [6872393] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DRC.2014.6872393

Low ON-resistance and high current GaN Vertical Electron Transistors with buried p-GaN layers. / Yeluri, Ramya; Lu, Jing; Browne, David; Hurni, Christophe A.; Chowdhury, Srabanti; Keller, Stacia; Speck, James S.; Mishra, Umesh K.

Device Research Conference - Conference Digest, DRC. Institute of Electrical and Electronics Engineers Inc., 2014. p. 253-254 6872393.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yeluri, R, Lu, J, Browne, D, Hurni, CA, Chowdhury, S, Keller, S, Speck, JS & Mishra, UK 2014, Low ON-resistance and high current GaN Vertical Electron Transistors with buried p-GaN layers. in Device Research Conference - Conference Digest, DRC., 6872393, Institute of Electrical and Electronics Engineers Inc., pp. 253-254, 72nd Device Research Conference, DRC 2014, Santa Barbara, CA, United States, 6/22/14. https://doi.org/10.1109/DRC.2014.6872393
Yeluri R, Lu J, Browne D, Hurni CA, Chowdhury S, Keller S et al. Low ON-resistance and high current GaN Vertical Electron Transistors with buried p-GaN layers. In Device Research Conference - Conference Digest, DRC. Institute of Electrical and Electronics Engineers Inc. 2014. p. 253-254. 6872393 https://doi.org/10.1109/DRC.2014.6872393
Yeluri, Ramya ; Lu, Jing ; Browne, David ; Hurni, Christophe A. ; Chowdhury, Srabanti ; Keller, Stacia ; Speck, James S. ; Mishra, Umesh K. / Low ON-resistance and high current GaN Vertical Electron Transistors with buried p-GaN layers. Device Research Conference - Conference Digest, DRC. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 253-254
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