Low-noise logic for mixed-mode VLSI circuits

Folded source-coupled (FSCL) and current-steering logic (CSL) techniques have been developed to complement static logic for application in high-precision, high-speed, mixed analog/digital CMOS integrated circuits. In contrasts to the full-supply voltage swing (ΔV_L = V_DD) characteristic of conventional CMOS logic, a significantly smaller swing (ΔV_L ≈ 0·2V_DD) is developed in both FSCL and CSL by manipulating a constant current drawn from the V_DD supply. Consequently, the measured power supply switching noise current spikes are less than 15 μA, a reduction of nearly two orders of magnitude compared with static logic. This feature allows higher performance to be realized from on-chip analog circuitry in mixed-mode applications using FSCL or CSL. Several synthesis techniques for FSCL gates are presented along with experimental results from FSCL and CSL prototypes integrated in a 2 μm p-well CMOS technology. The measured propagation delays of FSCL and CSL inverters are 700 ps and 400 ps, respectively, with corresponding power-delay products of 1·0 pJ and 0·4 pJ.