TY - GEN
T1 - Low energy motion estimation via selective aproximations
AU - Emre, Yunus
AU - Chakrabarti, Chaitali
PY - 2011
Y1 - 2011
N2 - This paper presents a novel sum of absolute difference (SAD) scheme that significantly reduces the energy consumption of the motion estimation kernel in video coders. The proposed scheme exploits the facts that most of the absolute difference (AD) calculations result in small values, and most of the large AD values do not contribute to the SAD values of the blocks that are selected. Thus the large AD values can be approximated, resulting in lower critical path delay and lower energy consumption of the SAD unit. In addition, the proposed scheme truncates one lower order bit and variants of this scheme implement sub-sampling to further reduce the energy consumption. Performance of the proposed technique is evaluated using the H.264 video encoding framework. Simulation results show 37.5% reduction in energy consumption at nominal voltage and 68% energy reduction for iso-throughput compared to the conventional implementation with only 0.06% drop in PSNR and 1.8% increase in compressed data rate. With an additional sub-sampling, the proposed scheme achieves 90% reduction in energy consumption with 0.6% reduction in PSNR and 6.5% increase in compressed data rate.
AB - This paper presents a novel sum of absolute difference (SAD) scheme that significantly reduces the energy consumption of the motion estimation kernel in video coders. The proposed scheme exploits the facts that most of the absolute difference (AD) calculations result in small values, and most of the large AD values do not contribute to the SAD values of the blocks that are selected. Thus the large AD values can be approximated, resulting in lower critical path delay and lower energy consumption of the SAD unit. In addition, the proposed scheme truncates one lower order bit and variants of this scheme implement sub-sampling to further reduce the energy consumption. Performance of the proposed technique is evaluated using the H.264 video encoding framework. Simulation results show 37.5% reduction in energy consumption at nominal voltage and 68% energy reduction for iso-throughput compared to the conventional implementation with only 0.06% drop in PSNR and 1.8% increase in compressed data rate. With an additional sub-sampling, the proposed scheme achieves 90% reduction in energy consumption with 0.6% reduction in PSNR and 6.5% increase in compressed data rate.
KW - Error Resiliency
KW - Low Energy Implementation
KW - Motion Estimation
UR - http://www.scopus.com/inward/record.url?scp=80055094423&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80055094423&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2011.6043266
DO - 10.1109/ASAP.2011.6043266
M3 - Conference contribution
AN - SCOPUS:80055094423
SN - 9781457712920
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 176
EP - 183
BT - Proceedings - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2011
T2 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2011
Y2 - 11 September 2011 through 14 September 2011
ER -