Low-cost test for large analog IC's

Sule Ozev, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.

Original languageEnglish (US)
Title of host publicationProceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages101-109
Number of pages9
ISBN (Electronic)076950325X, 9780769503257
DOIs
StatePublished - Jan 1 1999
Externally publishedYes
Event1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 - Albuquerque, United States
Duration: Nov 1 1999Nov 3 1999

Other

Other1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
CountryUnited States
CityAlbuquerque
Period11/1/9911/3/99

Fingerprint

Discrete Fourier transforms
Costs
Analog integrated circuits

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Ozev, S., & Orailoglu, A. (1999). Low-cost test for large analog IC's. In Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 (pp. 101-109). [802875] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFTVS.1999.802875

Low-cost test for large analog IC's. / Ozev, Sule; Orailoglu, Alex.

Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999. Institute of Electrical and Electronics Engineers Inc., 1999. p. 101-109 802875.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ozev, S & Orailoglu, A 1999, Low-cost test for large analog IC's. in Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999., 802875, Institute of Electrical and Electronics Engineers Inc., pp. 101-109, 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999, Albuquerque, United States, 11/1/99. https://doi.org/10.1109/DFTVS.1999.802875
Ozev S, Orailoglu A. Low-cost test for large analog IC's. In Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999. Institute of Electrical and Electronics Engineers Inc. 1999. p. 101-109. 802875 https://doi.org/10.1109/DFTVS.1999.802875
Ozev, Sule ; Orailoglu, Alex. / Low-cost test for large analog IC's. Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 101-109
@inproceedings{5e1cffaeab744e7b8133ff3171b34521,
title = "Low-cost test for large analog IC's",
abstract = "This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.",
author = "Sule Ozev and Alex Orailoglu",
year = "1999",
month = "1",
day = "1",
doi = "10.1109/DFTVS.1999.802875",
language = "English (US)",
pages = "101--109",
booktitle = "Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - Low-cost test for large analog IC's

AU - Ozev, Sule

AU - Orailoglu, Alex

PY - 1999/1/1

Y1 - 1999/1/1

N2 - This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.

AB - This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.

UR - http://www.scopus.com/inward/record.url?scp=84966356946&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84966356946&partnerID=8YFLogxK

U2 - 10.1109/DFTVS.1999.802875

DO - 10.1109/DFTVS.1999.802875

M3 - Conference contribution

SP - 101

EP - 109

BT - Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

PB - Institute of Electrical and Electronics Engineers Inc.

ER -