Low-cost test for large analog IC's

Sule Ozev; Alex Orailoglu

doi:10.1109/DFTVS.1999.802875

Low-cost test for large analog IC's

Sule Ozev, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.

Original language	English (US)
Title of host publication	Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	101-109
Number of pages	9
ISBN (Electronic)	076950325X, 9780769503257
DOIs	https://doi.org/10.1109/DFTVS.1999.802875
State	Published - 1999
Externally published	Yes
Event	1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 - Albuquerque, United States Duration: Nov 1 1999 → Nov 3 1999

Publication series

Name	Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

Other

Other	1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
Country/Territory	United States
City	Albuquerque
Period	11/1/99 → 11/3/99

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/DFTVS.1999.802875

Cite this

Ozev, S., & Orailoglu, A. (1999). Low-cost test for large analog IC's. In Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 (pp. 101-109). Article 802875 (Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFTVS.1999.802875

Low-cost test for large analog IC's. / Ozev, Sule; Orailoglu, Alex.
Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999. Institute of Electrical and Electronics Engineers Inc., 1999. p. 101-109 802875 (Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ozev, S & Orailoglu, A 1999, Low-cost test for large analog IC's. in Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999., 802875, Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999, Institute of Electrical and Electronics Engineers Inc., pp. 101-109, 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999, Albuquerque, United States, 11/1/99. https://doi.org/10.1109/DFTVS.1999.802875

Ozev S, Orailoglu A. Low-cost test for large analog IC's. In Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999. Institute of Electrical and Electronics Engineers Inc. 1999. p. 101-109. 802875. (Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999). doi: 10.1109/DFTVS.1999.802875

@inproceedings{5e1cffaeab744e7b8133ff3171b34521,

title = "Low-cost test for large analog IC's",

abstract = "This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.",

author = "Sule Ozev and Alex Orailoglu",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 ; Conference date: 01-11-1999 Through 03-11-1999",

year = "1999",

doi = "10.1109/DFTVS.1999.802875",

language = "English (US)",

series = "Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "101--109",

booktitle = "Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999",

}

TY - GEN

T1 - Low-cost test for large analog IC's

AU - Ozev, Sule

AU - Orailoglu, Alex

PY - 1999

Y1 - 1999

N2 - This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.

AB - This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.

UR - http://www.scopus.com/inward/record.url?scp=84966356946&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84966356946&partnerID=8YFLogxK

U2 - 10.1109/DFTVS.1999.802875

DO - 10.1109/DFTVS.1999.802875

M3 - Conference contribution

AN - SCOPUS:84966356946

T3 - Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

SP - 101

EP - 109

BT - Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

Y2 - 1 November 1999 through 3 November 1999

ER -

Low-cost test for large analog IC's

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this