Low-cost test for large analog IC's

Sule Ozev, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.

Original languageEnglish (US)
Title of host publicationIEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
PublisherIEEE
Pages101-109
Number of pages9
StatePublished - 1999
Externally publishedYes
EventProceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99) - Albueqeurque, NM, USA
Duration: Nov 1 1999Nov 3 1999

Other

OtherProceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99)
CityAlbueqeurque, NM, USA
Period11/1/9911/3/99

Fingerprint

Discrete Fourier transforms
Costs
Analog integrated circuits

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ozev, S., & Orailoglu, A. (1999). Low-cost test for large analog IC's. In IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (pp. 101-109). IEEE.

Low-cost test for large analog IC's. / Ozev, Sule; Orailoglu, Alex.

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE, 1999. p. 101-109.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ozev, S & Orailoglu, A 1999, Low-cost test for large analog IC's. in IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE, pp. 101-109, Proceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99), Albueqeurque, NM, USA, 11/1/99.
Ozev S, Orailoglu A. Low-cost test for large analog IC's. In IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE. 1999. p. 101-109
Ozev, Sule ; Orailoglu, Alex. / Low-cost test for large analog IC's. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE, 1999. pp. 101-109
@inproceedings{318d4f21ba484350a06672c14c1d8e0d,
title = "Low-cost test for large analog IC's",
abstract = "This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.",
author = "Sule Ozev and Alex Orailoglu",
year = "1999",
language = "English (US)",
pages = "101--109",
booktitle = "IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems",
publisher = "IEEE",

}

TY - GEN

T1 - Low-cost test for large analog IC's

AU - Ozev, Sule

AU - Orailoglu, Alex

PY - 1999

Y1 - 1999

N2 - This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.

AB - This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.

UR - http://www.scopus.com/inward/record.url?scp=0033320811&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033320811&partnerID=8YFLogxK

M3 - Conference contribution

SP - 101

EP - 109

BT - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

PB - IEEE

ER -