Abstract
This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems |
| Publisher | IEEE |
| Pages | 101-109 |
| Number of pages | 9 |
| State | Published - 1999 |
| Externally published | Yes |
| Event | Proceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99) - Albueqeurque, NM, USA Duration: Nov 1 1999 → Nov 3 1999 |
Other
| Other | Proceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99) |
|---|---|
| City | Albueqeurque, NM, USA |
| Period | 11/1/99 → 11/3/99 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering