TY - GEN
T1 - Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems
AU - Mao, Manqing
AU - Yang, Chengen
AU - Xu, Zihan
AU - Cao, Yu
AU - Chakrabarti, Chaitali
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/12/15
Y1 - 2014/12/15
N2 - Hybrid memory, where the DRAM acts as a buffer to the PRAM, is a promising configuration for main memory systems. It has the advantages of fast access time, high storage density and very low standby power. However, it also has reliability issues that need to be addressed. This paper focuses on low cost Error Control Coding (ECC)-based schemes for improving the reliability of hybrid memory. We propose three candidate systems that all guarantee block failure rate of 10-8 but differ in whether the DRAM and/or PRAM data get coded and the strength of the corresponding ECC code. The candidate systems are evaluated with respect to lifetime, Instruction Per Cycle (IPC) and energy. We show that (1) at lower Data Storage Time (DST), the proposed system which has different ECC schemes for DRAM and PRAM has the longest lifetime and one of the highest IPC; (2) at higher DST, stronger ECC codes are necessary for all the systems and longer lifetime can be achieved at the cost of decrease in IPC.
AB - Hybrid memory, where the DRAM acts as a buffer to the PRAM, is a promising configuration for main memory systems. It has the advantages of fast access time, high storage density and very low standby power. However, it also has reliability issues that need to be addressed. This paper focuses on low cost Error Control Coding (ECC)-based schemes for improving the reliability of hybrid memory. We propose three candidate systems that all guarantee block failure rate of 10-8 but differ in whether the DRAM and/or PRAM data get coded and the strength of the corresponding ECC code. The candidate systems are evaluated with respect to lifetime, Instruction Per Cycle (IPC) and energy. We show that (1) at lower Data Storage Time (DST), the proposed system which has different ECC schemes for DRAM and PRAM has the longest lifetime and one of the highest IPC; (2) at higher DST, stronger ECC codes are necessary for all the systems and longer lifetime can be achieved at the cost of decrease in IPC.
KW - DRAM+PRAM
KW - Hybrid main memory
KW - error correction codes
KW - reliability
UR - http://www.scopus.com/inward/record.url?scp=84920276890&partnerID=8YFLogxK
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U2 - 10.1109/SiPS.2014.6986076
DO - 10.1109/SiPS.2014.6986076
M3 - Conference contribution
AN - SCOPUS:84920276890
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
BT - IEEE Workshop on Signal Processing Systems, SiPS
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE Workshop on Signal Processing Systems, SiPS 2014
Y2 - 20 October 2014 through 22 October 2014
ER -