Low complexity out-of-order issue logic using static circuits

Siddhesh S. Mhambrey, Satendra K. Maurya, Lawrence T. Clark

Research output: Contribution to journalArticle

Abstract

In this paper a single-cycle issue queue circuit architecture that simplifies the wakeup and selection logic is proposed. The micro-architecture and fully static CMOS circuits are presented for a 32-entry queue that issues four instructions per cycle. The instruction-ready signals are divided into groups and processed in parallel to issue the four oldest ready instructions. The complete issue queue and prioritization logic requires 20 inversions, allowing simulated circuit operation at over 4 GHz in a foundry 45 nm SOI fabrication process.

Original languageEnglish (US)
Article number6144734
Pages (from-to)380-384
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number2
DOIs
StatePublished - 2013

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Networks (circuits)
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Fabrication

Keywords

  • CMOS digital integrated circuit
  • issue queue
  • microprocessor
  • out-of-order instruction issue
  • superscalar

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

Low complexity out-of-order issue logic using static circuits. / Mhambrey, Siddhesh S.; Maurya, Satendra K.; Clark, Lawrence T.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 2, 6144734, 2013, p. 380-384.

Research output: Contribution to journalArticle

Mhambrey, Siddhesh S. ; Maurya, Satendra K. ; Clark, Lawrence T. / Low complexity out-of-order issue logic using static circuits. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013 ; Vol. 21, No. 2. pp. 380-384.
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