Low complexity out-of-order issue logic using static circuits

Siddhesh S. Mhambrey, Satendra K. Maurya, Lawrence T. Clark

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper a single-cycle issue queue circuit architecture that simplifies the wakeup and selection logic is proposed. The micro-architecture and fully static CMOS circuits are presented for a 32-entry queue that issues four instructions per cycle. The instruction-ready signals are divided into groups and processed in parallel to issue the four oldest ready instructions. The complete issue queue and prioritization logic requires 20 inversions, allowing simulated circuit operation at over 4 GHz in a foundry 45 nm SOI fabrication process.

Original languageEnglish (US)
Article number6144734
Pages (from-to)380-384
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number2
DOIs
StatePublished - Jan 1 2013

Keywords

  • CMOS digital integrated circuit
  • issue queue
  • microprocessor
  • out-of-order instruction issue
  • superscalar

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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