LOTUS

Leakage optimization under timing uncertainty for standard-cell designs

Sarvesh Bhardwaj, Sarma Vrudhula, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper proposes a novel methodology for improving the leakage yield of digital circuits in the presence of process variations and under probabilistic timing constraints. The leakage minimization problem is formulated as a discrete optimization problem, where a suitable configuration for each gate in the circuit is selected from a standard-cell library consisting of different implementations of each type of gate. A function of mean and variance of the circuit leakage is minimized with constraint on a-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables in addition to gate sizes can provide significant power savings. We propose efficient techniques for computing delay and leakage power gradients which form the basis of the optimization algorithm. Results on various trade-offs such as between leakage and delay, and mean and variance of the leakage are discussed.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
Pages717-722
Number of pages6
DOIs
StatePublished - 2006
Event7th International Symposium on Quality Electronic Design, ISQED 2006 - San Jose, CA, United States
Duration: Mar 27 2006Mar 29 2006

Other

Other7th International Symposium on Quality Electronic Design, ISQED 2006
CountryUnited States
CitySan Jose, CA
Period3/27/063/29/06

Fingerprint

Networks (circuits)
Digital circuits
Threshold voltage
Uncertainty

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Bhardwaj, S., Vrudhula, S., & Cao, Y. (2006). LOTUS: Leakage optimization under timing uncertainty for standard-cell designs. In Proceedings - International Symposium on Quality Electronic Design, ISQED (pp. 717-722). [1613221] https://doi.org/10.1109/ISQED.2006.83

LOTUS : Leakage optimization under timing uncertainty for standard-cell designs. / Bhardwaj, Sarvesh; Vrudhula, Sarma; Cao, Yu.

Proceedings - International Symposium on Quality Electronic Design, ISQED. 2006. p. 717-722 1613221.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Bhardwaj, S, Vrudhula, S & Cao, Y 2006, LOTUS: Leakage optimization under timing uncertainty for standard-cell designs. in Proceedings - International Symposium on Quality Electronic Design, ISQED., 1613221, pp. 717-722, 7th International Symposium on Quality Electronic Design, ISQED 2006, San Jose, CA, United States, 3/27/06. https://doi.org/10.1109/ISQED.2006.83
Bhardwaj S, Vrudhula S, Cao Y. LOTUS: Leakage optimization under timing uncertainty for standard-cell designs. In Proceedings - International Symposium on Quality Electronic Design, ISQED. 2006. p. 717-722. 1613221 https://doi.org/10.1109/ISQED.2006.83
Bhardwaj, Sarvesh ; Vrudhula, Sarma ; Cao, Yu. / LOTUS : Leakage optimization under timing uncertainty for standard-cell designs. Proceedings - International Symposium on Quality Electronic Design, ISQED. 2006. pp. 717-722
@inproceedings{8a139e3e1d0e46498145e9ad161809f2,
title = "LOTUS: Leakage optimization under timing uncertainty for standard-cell designs",
abstract = "This paper proposes a novel methodology for improving the leakage yield of digital circuits in the presence of process variations and under probabilistic timing constraints. The leakage minimization problem is formulated as a discrete optimization problem, where a suitable configuration for each gate in the circuit is selected from a standard-cell library consisting of different implementations of each type of gate. A function of mean and variance of the circuit leakage is minimized with constraint on a-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables in addition to gate sizes can provide significant power savings. We propose efficient techniques for computing delay and leakage power gradients which form the basis of the optimization algorithm. Results on various trade-offs such as between leakage and delay, and mean and variance of the leakage are discussed.",
author = "Sarvesh Bhardwaj and Sarma Vrudhula and Yu Cao",
year = "2006",
doi = "10.1109/ISQED.2006.83",
language = "English (US)",
isbn = "0769525237",
pages = "717--722",
booktitle = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

}

TY - GEN

T1 - LOTUS

T2 - Leakage optimization under timing uncertainty for standard-cell designs

AU - Bhardwaj, Sarvesh

AU - Vrudhula, Sarma

AU - Cao, Yu

PY - 2006

Y1 - 2006

N2 - This paper proposes a novel methodology for improving the leakage yield of digital circuits in the presence of process variations and under probabilistic timing constraints. The leakage minimization problem is formulated as a discrete optimization problem, where a suitable configuration for each gate in the circuit is selected from a standard-cell library consisting of different implementations of each type of gate. A function of mean and variance of the circuit leakage is minimized with constraint on a-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables in addition to gate sizes can provide significant power savings. We propose efficient techniques for computing delay and leakage power gradients which form the basis of the optimization algorithm. Results on various trade-offs such as between leakage and delay, and mean and variance of the leakage are discussed.

AB - This paper proposes a novel methodology for improving the leakage yield of digital circuits in the presence of process variations and under probabilistic timing constraints. The leakage minimization problem is formulated as a discrete optimization problem, where a suitable configuration for each gate in the circuit is selected from a standard-cell library consisting of different implementations of each type of gate. A function of mean and variance of the circuit leakage is minimized with constraint on a-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables in addition to gate sizes can provide significant power savings. We propose efficient techniques for computing delay and leakage power gradients which form the basis of the optimization algorithm. Results on various trade-offs such as between leakage and delay, and mean and variance of the leakage are discussed.

UR - http://www.scopus.com/inward/record.url?scp=84886744801&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84886744801&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2006.83

DO - 10.1109/ISQED.2006.83

M3 - Conference contribution

SN - 0769525237

SN - 9780769525235

SP - 717

EP - 722

BT - Proceedings - International Symposium on Quality Electronic Design, ISQED

ER -