Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Xuejue Huang, Phillip Restle, Thomas Bucelot, Yu Cao, Tsu Jae King

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.

Original languageEnglish (US)
Title of host publicationProceedings of the Custom Integrated Circuits Conference
Pages19-22
Number of pages4
StatePublished - 2002
Externally publishedYes
EventIEEE 2002 Custom Integrated Circuits Conference - Orlando, FL, United States
Duration: May 12 2002May 15 2002

Other

OtherIEEE 2002 Custom Integrated Circuits Conference
CountryUnited States
CityOrlando, FL
Period5/12/025/15/02

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Huang, X., Restle, P., Bucelot, T., Cao, Y., & King, T. J. (2002). Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. In Proceedings of the Custom Integrated Circuits Conference (pp. 19-22)