Bias temperature instability (BTI) is the dominant source of aging in nanoscale transistors. Recent works show the role of charge trapping/de-trapping (T-D) in BTI through discrete Vth shifts, with the degradation exhibiting an excessive amount of randomness. Furthermore, modern circuits employ dynamic voltage scaling (DVS) where Vdd is tuned, complicating the aging effect. It becomes challenging to predict long-term aging in an actual circuit under statistical variation and DVS. To accurately predict the degradation in these circumstances, this work (1) examines the principles of T-D, thereby proposing static and cycle-to-cycle (dynamic) models under voltage tuning in DVS; (2) presents a long-term model, estimating a tight upper bound of dynamic aging; (3) comprehensively validates the new set of models with 65nm silicon data. The proposed aging models accurately capture the recovery behavior in dynamic operations, reducing the unnecessary margin and enhancing the simulation efficiency for aging estimation during the design stage.