Logarithmic modeling of BTI under dynamic circuit operation

Static, dynamic and long-term prediction

Jyothi B. Velamala, Ketul B. Sutaria, Hirofumi Shimuzu, Hiromitsu Awano, Takashi Sato, Gilson Wirth, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Bias temperature instability (BTI) is the dominant source of aging in nanoscale transistors. Recent works show the role of charge trapping/de-trapping (T-D) in BTI through discrete Vth shifts, with the degradation exhibiting an excessive amount of randomness. Furthermore, modern circuits employ dynamic voltage scaling (DVS) where Vdd is tuned, complicating the aging effect. It becomes challenging to predict long-term aging in an actual circuit under statistical variation and DVS. To accurately predict the degradation in these circumstances, this work (1) examines the principles of T-D, thereby proposing static and cycle-to-cycle (dynamic) models under voltage tuning in DVS; (2) presents a long-term model, estimating a tight upper bound of dynamic aging; (3) comprehensively validates the new set of models with 65nm silicon data. The proposed aging models accurately capture the recovery behavior in dynamic operations, reducing the unnecessary margin and enhancing the simulation efficiency for aging estimation during the design stage.

Original languageEnglish (US)
Title of host publicationIEEE International Reliability Physics Symposium Proceedings
DOIs
StatePublished - 2013
Event2013 IEEE International Reliability Physics Symposium, IRPS 2013 - Monterey, CA, United States
Duration: Apr 14 2013Apr 18 2013

Other

Other2013 IEEE International Reliability Physics Symposium, IRPS 2013
CountryUnited States
CityMonterey, CA
Period4/14/134/18/13

Fingerprint

Aging of materials
Networks (circuits)
Temperature
Degradation
Charge trapping
Dynamic models
Transistors
Tuning
Recovery
Silicon
Electric potential
Voltage scaling

Keywords

  • compact modeling
  • DVS
  • negative bias temperature instability
  • statistical variations
  • Trapping/de-trapping

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Velamala, J. B., Sutaria, K. B., Shimuzu, H., Awano, H., Sato, T., Wirth, G., & Cao, Y. (2013). Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction. In IEEE International Reliability Physics Symposium Proceedings [6532063] https://doi.org/10.1109/IRPS.2013.6532063

Logarithmic modeling of BTI under dynamic circuit operation : Static, dynamic and long-term prediction. / Velamala, Jyothi B.; Sutaria, Ketul B.; Shimuzu, Hirofumi; Awano, Hiromitsu; Sato, Takashi; Wirth, Gilson; Cao, Yu.

IEEE International Reliability Physics Symposium Proceedings. 2013. 6532063.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Velamala, JB, Sutaria, KB, Shimuzu, H, Awano, H, Sato, T, Wirth, G & Cao, Y 2013, Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction. in IEEE International Reliability Physics Symposium Proceedings., 6532063, 2013 IEEE International Reliability Physics Symposium, IRPS 2013, Monterey, CA, United States, 4/14/13. https://doi.org/10.1109/IRPS.2013.6532063
Velamala JB, Sutaria KB, Shimuzu H, Awano H, Sato T, Wirth G et al. Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction. In IEEE International Reliability Physics Symposium Proceedings. 2013. 6532063 https://doi.org/10.1109/IRPS.2013.6532063
Velamala, Jyothi B. ; Sutaria, Ketul B. ; Shimuzu, Hirofumi ; Awano, Hiromitsu ; Sato, Takashi ; Wirth, Gilson ; Cao, Yu. / Logarithmic modeling of BTI under dynamic circuit operation : Static, dynamic and long-term prediction. IEEE International Reliability Physics Symposium Proceedings. 2013.
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