Localization of gate bias induced threshold voltage degradation in a-Si: H TFTs

Rahul Shringarpure, Sameer Venugopal, Lawrence T. Clark, David Allee, Edward Bawolek

Research output: Contribution to journalArticle

19 Citations (Scopus)

Abstract

This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage (Vth) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent Vth shift mechanism. Based on the observations, a charge-based expression for Vth shift is derived.

Original languageEnglish (US)
Pages (from-to)93-95
Number of pages3
JournalIEEE Electron Device Letters
Volume29
Issue number1
DOIs
StatePublished - Jan 2008

Fingerprint

Threshold voltage
Degradation
Drain current
Thin film transistors
Amorphous silicon
Electric potential
Direction compound

Keywords

  • Amorphous silicon thin film transistors (a-Si:H TFTs)
  • Circuit simulation
  • Display technology
  • Spice
  • Threshold voltage degradation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Localization of gate bias induced threshold voltage degradation in a-Si : H TFTs. / Shringarpure, Rahul; Venugopal, Sameer; Clark, Lawrence T.; Allee, David; Bawolek, Edward.

In: IEEE Electron Device Letters, Vol. 29, No. 1, 01.2008, p. 93-95.

Research output: Contribution to journalArticle

Shringarpure, Rahul ; Venugopal, Sameer ; Clark, Lawrence T. ; Allee, David ; Bawolek, Edward. / Localization of gate bias induced threshold voltage degradation in a-Si : H TFTs. In: IEEE Electron Device Letters. 2008 ; Vol. 29, No. 1. pp. 93-95.
@article{abf6b088b8f14ef18c84856c13544b92,
title = "Localization of gate bias induced threshold voltage degradation in a-Si: H TFTs",
abstract = "This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage (Vth) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent Vth shift mechanism. Based on the observations, a charge-based expression for Vth shift is derived.",
keywords = "Amorphous silicon thin film transistors (a-Si:H TFTs), Circuit simulation, Display technology, Spice, Threshold voltage degradation",
author = "Rahul Shringarpure and Sameer Venugopal and Clark, {Lawrence T.} and David Allee and Edward Bawolek",
year = "2008",
month = "1",
doi = "10.1109/LED.2007.911609",
language = "English (US)",
volume = "29",
pages = "93--95",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - Localization of gate bias induced threshold voltage degradation in a-Si

T2 - H TFTs

AU - Shringarpure, Rahul

AU - Venugopal, Sameer

AU - Clark, Lawrence T.

AU - Allee, David

AU - Bawolek, Edward

PY - 2008/1

Y1 - 2008/1

N2 - This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage (Vth) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent Vth shift mechanism. Based on the observations, a charge-based expression for Vth shift is derived.

AB - This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage (Vth) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent Vth shift mechanism. Based on the observations, a charge-based expression for Vth shift is derived.

KW - Amorphous silicon thin film transistors (a-Si:H TFTs)

KW - Circuit simulation

KW - Display technology

KW - Spice

KW - Threshold voltage degradation

UR - http://www.scopus.com/inward/record.url?scp=37549007863&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=37549007863&partnerID=8YFLogxK

U2 - 10.1109/LED.2007.911609

DO - 10.1109/LED.2007.911609

M3 - Article

AN - SCOPUS:37549007863

VL - 29

SP - 93

EP - 95

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 1

ER -