Localization of gate bias induced threshold voltage degradation in a-Si:H TFTs

Rahul Shringarpure, Sameer Venugopal, Lawrence T. Clark, David Allee, Edward Bawolek

Research output: Contribution to journalArticle

21 Scopus citations

Abstract

This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage (Vth) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent Vth shift mechanism. Based on the observations, a charge-based expression for Vth shift is derived.

Original languageEnglish (US)
Pages (from-to)93-95
Number of pages3
JournalIEEE Electron Device Letters
Volume29
Issue number1
DOIs
StatePublished - Jan 1 2008

Keywords

  • Amorphous silicon thin film transistors (a-Si:H TFTs)
  • Circuit simulation
  • Display technology
  • Spice
  • Threshold voltage degradation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Localization of gate bias induced threshold voltage degradation in a-Si:H TFTs'. Together they form a unique fingerprint.

  • Cite this