TY - JOUR
T1 - Linear-programming-based techniques for synthesis of network-on-chip architectures
AU - Srinivasan, Krishnan
AU - Chatha, Karam S.
AU - Konjevod, Goran
N1 - Funding Information:
Manuscript received August 22, 2004; revised December 15, 2004 and July 29, 2005. This work was supported in part by the National Science Foundation under CAREER Award CCF-0546462, IIS-0308268 and in part by Consortium for Embedded Systems.
PY - 2006/4
Y1 - 2006/4
N2 - Application-specific system-on-chip (SoC) design offers the opportunity for incorporating custom network-on-chip (NoC) architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel mixed integer linear programming (MILP) formulations for synthesis of custom NoC architectures. The optimization objective of the techniques is to minimize the power consumption subject to the performance constraints. We present a two-stage approach for solving the custom NoC synthesis problem. The power consumption of the NoC architecture is determined by both the physical links and routers. The power consumption of a physical link is dependent upon the length of the link, which in turn, is governed by the layout of the SoC. Therefore, in the first stage, we address the floorplanning problem that determines the locations of the various cores and the routers. In the second stage, we utilize the floorplan from the first stage to generate topology of the NoC and the routes for the various traffic traces. We also present a clustering-based heuristic technique for the second stage to reduce the run times of the MILP formulation. We analyze the quality of the results and solution times of the proposed techniques by extensive experimentation with realistic benchmarks and comparisons with regular mesh-based NoC architectures.
AB - Application-specific system-on-chip (SoC) design offers the opportunity for incorporating custom network-on-chip (NoC) architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel mixed integer linear programming (MILP) formulations for synthesis of custom NoC architectures. The optimization objective of the techniques is to minimize the power consumption subject to the performance constraints. We present a two-stage approach for solving the custom NoC synthesis problem. The power consumption of the NoC architecture is determined by both the physical links and routers. The power consumption of a physical link is dependent upon the length of the link, which in turn, is governed by the layout of the SoC. Therefore, in the first stage, we address the floorplanning problem that determines the locations of the various cores and the routers. In the second stage, we utilize the floorplan from the first stage to generate topology of the NoC and the routes for the various traffic traces. We also present a clustering-based heuristic technique for the second stage to reduce the run times of the MILP formulation. We analyze the quality of the results and solution times of the proposed techniques by extensive experimentation with realistic benchmarks and comparisons with regular mesh-based NoC architectures.
KW - Design automation
KW - Integrated circuit interconnection
KW - Multiprocessor interconnection
UR - http://www.scopus.com/inward/record.url?scp=33746590812&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33746590812&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2006.871762
DO - 10.1109/TVLSI.2006.871762
M3 - Article
AN - SCOPUS:33746590812
SN - 1063-8210
VL - 14
SP - 407
EP - 420
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 4
M1 - 1637470
ER -