Linear programming based techniques for synthesis of Network-on-Chip architectures

Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod

Research output: Chapter in Book/Report/Conference proceedingConference contribution

53 Scopus citations

Abstract

Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel linear programming based techniques for synthesis of custom NoC architectures. In the nanoscale regime, low power consumption would continue to be an important design goal. We first discuss an optimal mixed integer linear programming (MILP) formulation that synthesizes a low power NoC architecture subject to the performance constraints. The MILP formulation is limited by large run times. We next present heuristic techniques that exploit clustering, and 0-1 constraint relaxation to reduce the run times of the formulation. The techniques minimize power as the primary goal, and minimize the number of routers (area) as a secondary goal. We present an analysis of the quality of the results and the solution times of the proposed techniques by extensive experimentation with the realistic benchmarks. The clustering based heuristic generates results whose power consumption is within 11% of the MILP solutions and its average run time is 171.1 seconds. The average run time of the relaxation and rounding based techniques is less than 2 seconds, and the power consumption of their solutions is within 58% of the MILP result.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Pages422-429
Number of pages8
StatePublished - 2004
EventProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States
Duration: Oct 11 2004Oct 13 2004

Other

OtherProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
CountryUnited States
CitySan Jose, CA
Period10/11/0410/13/04

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

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