Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS

Trevor J. Thornton, Chaojiang Li, Payam Mehr

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Integrated n-channel NFET-MESFET cascode power amplifiers (PAs) have been fabricated using a 45 nm SOI CMOS technology optimized for 5G applications. The cascode architecture combines the RF performance of the 40nm gate length NFET (fmax > 340 GHz) with the high voltage capability (VDD > 10 V) of the SOI MESFET. Load-pull measurements at 5.8 GHz confirm that a PA with 18 dBm saturated output power, >21dB gain, and >50% power added efficiency (PAE) can support 64QAM signals with 3% error vector magnitude and 25% average PAE at 6dB backed off power levels. These results suggest that an NFET-MESFET cascode PA might be suitable for low-cost 5G picocell/femtocell applications without the need for digital pre-distortion.

Original languageEnglish (US)
Title of host publication2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728135236
DOIs
StatePublished - Oct 14 2019
Event2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 - San Jose, United States
Duration: Oct 14 2019Oct 17 2019

Publication series

Name2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

Conference

Conference2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
CountryUnited States
CitySan Jose
Period10/14/1910/17/19

Keywords

  • MESFET
  • error vector magnitude
  • fifth generation (5G) mobile
  • power amplifiers
  • silicon-on-insulator technology

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Electronic, Optical and Magnetic Materials

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