Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS

Trevor J. Thornton; Chaojiang Li; Payam Mehr

doi:10.1109/S3S46989.2019.9320709

Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS

Trevor J. Thornton, Chaojiang Li, Payam Mehr

Electrical, Computer, and Energy Engineering, School of (IAFSE-ECEE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Integrated n-channel NFET-MESFET cascode power amplifiers (PAs) have been fabricated using a 45 nm SOI CMOS technology optimized for 5G applications. The cascode architecture combines the RF performance of the 40nm gate length NFET (fmax > 340 GHz) with the high voltage capability (VDD > 10 V) of the SOI MESFET. Load-pull measurements at 5.8 GHz confirm that a PA with 18 dBm saturated output power, >21dB gain, and >50% power added efficiency (PAE) can support 64QAM signals with 3% error vector magnitude and 25% average PAE at 6dB backed off power levels. These results suggest that an NFET-MESFET cascode PA might be suitable for low-cost 5G picocell/femtocell applications without the need for digital pre-distortion.

Original language	English (US)
Title of host publication	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728135236
DOIs	https://doi.org/10.1109/S3S46989.2019.9320709
State	Published - Oct 14 2019
Event	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 - San Jose, United States Duration: Oct 14 2019 → Oct 17 2019

Publication series

Name	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

Conference

Conference	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Country/Territory	United States
City	San Jose
Period	10/14/19 → 10/17/19

Keywords

MESFET
error vector magnitude
fifth generation (5G) mobile
power amplifiers
silicon-on-insulator technology

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/S3S46989.2019.9320709

Cite this

Thornton, T. J., Li, C., & Mehr, P. (2019). Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS. In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 Article 9320709 (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S46989.2019.9320709

Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS. / Thornton, Trevor J.; Li, Chaojiang; Mehr, Payam.
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9320709 (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Thornton, TJ, Li, C & Mehr, P 2019, Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS. in 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019., 9320709, 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, San Jose, United States, 10/14/19. https://doi.org/10.1109/S3S46989.2019.9320709

Thornton TJ, Li C, Mehr P. Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS. In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 9320709. (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019). doi: 10.1109/S3S46989.2019.9320709

Thornton, Trevor J. ; Li, Chaojiang ; Mehr, Payam. / Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS. 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019).

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title = "Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS",

abstract = "Integrated n-channel NFET-MESFET cascode power amplifiers (PAs) have been fabricated using a 45 nm SOI CMOS technology optimized for 5G applications. The cascode architecture combines the RF performance of the 40nm gate length NFET (fmax > 340 GHz) with the high voltage capability (VDD > 10 V) of the SOI MESFET. Load-pull measurements at 5.8 GHz confirm that a PA with 18 dBm saturated output power, >21dB gain, and >50% power added efficiency (PAE) can support 64QAM signals with 3% error vector magnitude and 25% average PAE at 6dB backed off power levels. These results suggest that an NFET-MESFET cascode PA might be suitable for low-cost 5G picocell/femtocell applications without the need for digital pre-distortion.",

keywords = "MESFET, error vector magnitude, fifth generation (5G) mobile, power amplifiers, silicon-on-insulator technology",

author = "Thornton, {Trevor J.} and Chaojiang Li and Payam Mehr",

note = "Funding Information: This work was supported, in part, by NSF award number NNCI – 1542160. Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 ; Conference date: 14-10-2019 Through 17-10-2019",

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N2 - Integrated n-channel NFET-MESFET cascode power amplifiers (PAs) have been fabricated using a 45 nm SOI CMOS technology optimized for 5G applications. The cascode architecture combines the RF performance of the 40nm gate length NFET (fmax > 340 GHz) with the high voltage capability (VDD > 10 V) of the SOI MESFET. Load-pull measurements at 5.8 GHz confirm that a PA with 18 dBm saturated output power, >21dB gain, and >50% power added efficiency (PAE) can support 64QAM signals with 3% error vector magnitude and 25% average PAE at 6dB backed off power levels. These results suggest that an NFET-MESFET cascode PA might be suitable for low-cost 5G picocell/femtocell applications without the need for digital pre-distortion.

AB - Integrated n-channel NFET-MESFET cascode power amplifiers (PAs) have been fabricated using a 45 nm SOI CMOS technology optimized for 5G applications. The cascode architecture combines the RF performance of the 40nm gate length NFET (fmax > 340 GHz) with the high voltage capability (VDD > 10 V) of the SOI MESFET. Load-pull measurements at 5.8 GHz confirm that a PA with 18 dBm saturated output power, >21dB gain, and >50% power added efficiency (PAE) can support 64QAM signals with 3% error vector magnitude and 25% average PAE at 6dB backed off power levels. These results suggest that an NFET-MESFET cascode PA might be suitable for low-cost 5G picocell/femtocell applications without the need for digital pre-distortion.

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Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS

Abstract

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