Limits of Nano-Gate Fabrication

David R. Allee, Alec N. Broers, R. Fabian W. Pease

Research output: Contribution to journalArticle

12 Scopus citations

Abstract

This paper reviews the limits of nanometer scale gate electrode (nano-gate) fabrication. The technology to fabricate nano-gates has become increasingly important in recent years as the scaling limits of conventional electronic devices and the quantum effects of novel devices are investigated. Consistant with the technology used to fabricate virtually all of the smallest devices to date, the emphasis is on the resolution limits of electron beam lithography and associated ultrahigh resolution resists. Recent results of directly patterning Si02 with nanometer scale resolution by e-beam exposure through a sacrificial layer are also presented. Finally, because the high resistance normally associated with nanometer scale electrodes seriously limits the performance of high frequency devices, various techniques to reduce the gate resistance are compared.

Original languageEnglish (US)
Pages (from-to)1093-1105
Number of pages13
JournalProceedings of the IEEE
Volume79
Issue number8
DOIs
StatePublished - Jan 1 1991
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Limits of Nano-Gate Fabrication'. Together they form a unique fingerprint.

  • Cite this

    Allee, D. R., Broers, A. N., & Pease, R. F. W. (1991). Limits of Nano-Gate Fabrication. Proceedings of the IEEE, 79(8), 1093-1105. https://doi.org/10.1109/5.92069