Leveraging all-spin logic to improve hardware security

Qutaiba Alasad, Jiann Yuan, Deliang Fan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

Due to the globalization of Integrated Circuit (IC) design in the semiconductor industry and the outsourcing of chip manufacturing, third Party Intellectual Properties (3PIPs) become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware trojans. A designer has to employ a strong technique to thwart such attacks, e.g. using Strong Logic Locking method [1]. But, such technique cannot be used to protect some circuits since the inserted key-gates rely on the topology of the circuit. Also, it requires higher power, delay, and area overheads compared to other techniques. In this paper, we present the use of spintronic devices to help protect ICs with less performance overhead. We then evaluate the proposed design based on security metric and performance overhead. One of the best spintronic device candidates is the All Spin Logic due to its unique properties: small area, no spin-charge signal conversion, and its compatibility with conventional CMOS technology.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PublisherAssociation for Computing Machinery
Pages491-494
Number of pages4
ISBN (Electronic)9781450349727
DOIs
StatePublished - May 10 2017
Externally publishedYes
Event27th Great Lakes Symposium on VLSI, GLSVLSI 2017 - Banff, Canada
Duration: May 10 2017May 12 2017

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
VolumePart F127756

Other

Other27th Great Lakes Symposium on VLSI, GLSVLSI 2017
Country/TerritoryCanada
CityBanff
Period5/10/175/12/17

ASJC Scopus subject areas

  • Engineering(all)

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