TY - GEN
T1 - Leveraging all-spin logic to improve hardware security
AU - Alasad, Qutaiba
AU - Yuan, Jiann
AU - Fan, Deliang
PY - 2017/5/10
Y1 - 2017/5/10
N2 - Due to the globalization of Integrated Circuit (IC) design in the semiconductor industry and the outsourcing of chip manufacturing, third Party Intellectual Properties (3PIPs) become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware trojans. A designer has to employ a strong technique to thwart such attacks, e.g. using Strong Logic Locking method [1]. But, such technique cannot be used to protect some circuits since the inserted key-gates rely on the topology of the circuit. Also, it requires higher power, delay, and area overheads compared to other techniques. In this paper, we present the use of spintronic devices to help protect ICs with less performance overhead. We then evaluate the proposed design based on security metric and performance overhead. One of the best spintronic device candidates is the All Spin Logic due to its unique properties: small area, no spin-charge signal conversion, and its compatibility with conventional CMOS technology.
AB - Due to the globalization of Integrated Circuit (IC) design in the semiconductor industry and the outsourcing of chip manufacturing, third Party Intellectual Properties (3PIPs) become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware trojans. A designer has to employ a strong technique to thwart such attacks, e.g. using Strong Logic Locking method [1]. But, such technique cannot be used to protect some circuits since the inserted key-gates rely on the topology of the circuit. Also, it requires higher power, delay, and area overheads compared to other techniques. In this paper, we present the use of spintronic devices to help protect ICs with less performance overhead. We then evaluate the proposed design based on security metric and performance overhead. One of the best spintronic device candidates is the All Spin Logic due to its unique properties: small area, no spin-charge signal conversion, and its compatibility with conventional CMOS technology.
UR - http://www.scopus.com/inward/record.url?scp=85021207912&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85021207912&partnerID=8YFLogxK
U2 - 10.1145/3060403.3060471
DO - 10.1145/3060403.3060471
M3 - Conference contribution
AN - SCOPUS:85021207912
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 491
EP - 494
BT - GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PB - Association for Computing Machinery
T2 - 27th Great Lakes Symposium on VLSI, GLSVLSI 2017
Y2 - 10 May 2017 through 12 May 2017
ER -