Leakage reduction through optimization of regular layout parameters

Anupama R. Subramaniam, Ritu Singhal, Chi Chao Wang, Yu Cao

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Regular layouts that follow restrictive design rules are essential to robust CMOS design in order to alleviate many manufacturing induced effects, such as the effect of non-rectangular gate (NRG) due to sub-wavelength lithograph. NRG dramatically increases the leakage current by more than 15X compared to that of ideal physical layout. To mitigate such a penalty, we developed a technique to optimize regular layout through restrictive design rule parameters and to benchmark post-lithography circuit performance. We propose a procedure to systematically optimize key layout parameters in regular layout to minimize the leakage energy with minimal over head to active energy, circuit speed and area. The proposed layout optimization technique is demonstrated with a 65 nm technology and projected for 45 nm and 32 nm technology nodes. Experimental results show that more than 70% reduction in leakage can be achieved with area penalty of ∼10% and 912% overhead on circuit speed and active energy.

Original languageEnglish (US)
Pages (from-to)25-33
Number of pages9
JournalMicroelectronics Journal
Volume43
Issue number1
DOIs
StatePublished - Jan 2012
Externally publishedYes

Keywords

  • Critical dimension
  • Leakage
  • Non-rectangular gate
  • Process variation
  • Regular layout optimization
  • Restrictive design rules

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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