TY - JOUR
T1 - Leakage power and circuit aging cooptimization by gate replacement techniques
AU - Wang, Yu
AU - Chen, Xiaoming
AU - Wang, Wenping
AU - Cao, Yu
AU - Xie, Yuan
AU - Yang, Huazhong
N1 - Funding Information:
Manuscript received June 22, 2009; revised September 28, 2009 and November 12, 2009. First published January 12, 2010; current version published March 23, 2011. This work was supported by National Key Technological Program of China under Contract 2008ZX01035-001, by the National Natural Science Foundation of China under Contract 60870001 and Contract 90707002, by the National 863 Project of China under Contract 2009AA01Z130, by Tsinghua National Laboratory for Information Science and Technology Cross-Discipline Foundation. The work of Y. Cao was supported in part by GSRC/SRC. The work of Y. Xie was supported in part by grants from NSF 0643902, 0702617, and an SRC Grant.
PY - 2011/4
Y1 - 2011/4
N2 - As technology scales, the aging effect caused by negative bias temperature instability (NBTI) has become a major reliability concern. In the mean time, reducing leakage power remains to be one of the key design goals. Because both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input vectors, input vector control (IVC) technique could be adopted to reduce the leakage power and mitigate NBTI-induced degradation. The IVC technique, however, is ineffective for larger circuits. Consequently, in this paper, we propose two gate replacement algorithms [direct gate replacement (DGR) algorithm and divide and conquer-based gate replacement (DCBGR) algorithm], together with optimal input vector selection, to simultaneously reduce the leakage power and mitigate NBTI-induced degradation. Our experimental results on 23 benchmark circuits reveal the following. 1) Both DGR and DCBGR algorithms outperform pure IVC technique by 15%-30% with 5% delay relaxation for three different design goals: leakage power reduction only, NBTI mitigation only, and leakage/NBTI cooptimization. 2) The DCBGR algorithm leads to better optimization results and save on average more than 10 × runtime compared to the DGR algorithm. 3) The area overhead for leakage reduction is much more than that for NBTI mitigation.
AB - As technology scales, the aging effect caused by negative bias temperature instability (NBTI) has become a major reliability concern. In the mean time, reducing leakage power remains to be one of the key design goals. Because both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input vectors, input vector control (IVC) technique could be adopted to reduce the leakage power and mitigate NBTI-induced degradation. The IVC technique, however, is ineffective for larger circuits. Consequently, in this paper, we propose two gate replacement algorithms [direct gate replacement (DGR) algorithm and divide and conquer-based gate replacement (DCBGR) algorithm], together with optimal input vector selection, to simultaneously reduce the leakage power and mitigate NBTI-induced degradation. Our experimental results on 23 benchmark circuits reveal the following. 1) Both DGR and DCBGR algorithms outperform pure IVC technique by 15%-30% with 5% delay relaxation for three different design goals: leakage power reduction only, NBTI mitigation only, and leakage/NBTI cooptimization. 2) The DCBGR algorithm leads to better optimization results and save on average more than 10 × runtime compared to the DGR algorithm. 3) The area overhead for leakage reduction is much more than that for NBTI mitigation.
KW - Gate replacement
KW - internal node control (INC)
KW - leakage power
KW - negative bias temperature instability (NBTI)
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U2 - 10.1109/TVLSI.2009.2037637
DO - 10.1109/TVLSI.2009.2037637
M3 - Article
AN - SCOPUS:79953078540
VL - 19
SP - 615
EP - 628
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 4
M1 - 5378474
ER -