Leakage minimization of nano-scale circuits in the presence of systematic and random variations

Sarvesh Bhardwaj, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Citations (Scopus)

Abstract

This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(|N| 2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages541-546
Number of pages6
StatePublished - 2005
Event42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States
Duration: Jun 13 2005Jun 17 2005

Other

Other42nd Design Automation Conference, DAC 2005
CountryUnited States
CityAnaheim, CA
Period6/13/056/17/05

Fingerprint

Networks (circuits)
Convex optimization
Wire

Keywords

  • Geometric Programming
  • Leakage
  • Optimization
  • Statistical

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Bhardwaj, S., & Vrudhula, S. (2005). Leakage minimization of nano-scale circuits in the presence of systematic and random variations. In Proceedings - Design Automation Conference (pp. 541-546). [32.4]

Leakage minimization of nano-scale circuits in the presence of systematic and random variations. / Bhardwaj, Sarvesh; Vrudhula, Sarma.

Proceedings - Design Automation Conference. 2005. p. 541-546 32.4.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Bhardwaj, S & Vrudhula, S 2005, Leakage minimization of nano-scale circuits in the presence of systematic and random variations. in Proceedings - Design Automation Conference., 32.4, pp. 541-546, 42nd Design Automation Conference, DAC 2005, Anaheim, CA, United States, 6/13/05.
Bhardwaj S, Vrudhula S. Leakage minimization of nano-scale circuits in the presence of systematic and random variations. In Proceedings - Design Automation Conference. 2005. p. 541-546. 32.4
Bhardwaj, Sarvesh ; Vrudhula, Sarma. / Leakage minimization of nano-scale circuits in the presence of systematic and random variations. Proceedings - Design Automation Conference. 2005. pp. 541-546
@inproceedings{74fb35c5f6b345939bd8dd18a4c22c5c,
title = "Leakage minimization of nano-scale circuits in the presence of systematic and random variations",
abstract = "This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(|N| 2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.",
keywords = "Geometric Programming, Leakage, Optimization, Statistical",
author = "Sarvesh Bhardwaj and Sarma Vrudhula",
year = "2005",
language = "English (US)",
pages = "541--546",
booktitle = "Proceedings - Design Automation Conference",

}

TY - GEN

T1 - Leakage minimization of nano-scale circuits in the presence of systematic and random variations

AU - Bhardwaj, Sarvesh

AU - Vrudhula, Sarma

PY - 2005

Y1 - 2005

N2 - This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(|N| 2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.

AB - This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(|N| 2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.

KW - Geometric Programming

KW - Leakage

KW - Optimization

KW - Statistical

UR - http://www.scopus.com/inward/record.url?scp=27944502914&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=27944502914&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:27944502914

SP - 541

EP - 546

BT - Proceedings - Design Automation Conference

ER -