Leakage minimization of nano-scale circuits in the presence of systematic and random variations

Sarvesh Bhardwaj, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Scopus citations

Abstract

This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(|N| 2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages541-546
Number of pages6
StatePublished - 2005
Event42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States
Duration: Jun 13 2005Jun 17 2005

Other

Other42nd Design Automation Conference, DAC 2005
CountryUnited States
CityAnaheim, CA
Period6/13/056/17/05

Keywords

  • Geometric Programming
  • Leakage
  • Optimization
  • Statistical

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Fingerprint Dive into the research topics of 'Leakage minimization of nano-scale circuits in the presence of systematic and random variations'. Together they form a unique fingerprint.

  • Cite this

    Bhardwaj, S., & Vrudhula, S. (2005). Leakage minimization of nano-scale circuits in the presence of systematic and random variations. In Proceedings - Design Automation Conference (pp. 541-546). [32.4]