Abstract
This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(|N| 2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.
Original language | English (US) |
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Title of host publication | Proceedings - Design Automation Conference |
Pages | 541-546 |
Number of pages | 6 |
State | Published - 2005 |
Event | 42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States Duration: Jun 13 2005 → Jun 17 2005 |
Other
Other | 42nd Design Automation Conference, DAC 2005 |
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Country/Territory | United States |
City | Anaheim, CA |
Period | 6/13/05 → 6/17/05 |
Keywords
- Geometric Programming
- Leakage
- Optimization
- Statistical
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering