TY - GEN
T1 - LCSRAM
T2 - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
AU - Badrudduza, Sayeed A.
AU - Samson, Giby
AU - Clark, Lawrence T.
PY - 2007/12/1
Y1 - 2007/12/1
N2 - Highly scaled processes increase leakage and transistor variations, both of which are problematic for SRAM, which is pervasive in modern CMOS integrated circuits. Here, a six transistor SRAM cell is presented that does not suffer from reduced stability when reading. The cell also resides in a low leakage, voltage collapsed, low standby power mode when not being accessed. The cell circuit topology, layout, and impact on memory design are described. Simulation of operation on 130 and 90 nm technologies and with predictive technology models for 65 and 45 nm technologies demonstrate the leakage reduction and measurement on 130 nm demonstrates improved read stability.
AB - Highly scaled processes increase leakage and transistor variations, both of which are problematic for SRAM, which is pervasive in modern CMOS integrated circuits. Here, a six transistor SRAM cell is presented that does not suffer from reduced stability when reading. The cell also resides in a low leakage, voltage collapsed, low standby power mode when not being accessed. The cell circuit topology, layout, and impact on memory design are described. Simulation of operation on 130 and 90 nm technologies and with predictive technology models for 65 and 45 nm technologies demonstrate the leakage reduction and measurement on 130 nm demonstrates improved read stability.
UR - http://www.scopus.com/inward/record.url?scp=47749148980&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=47749148980&partnerID=8YFLogxK
U2 - 10.1109/VLSID.2007.96
DO - 10.1109/VLSID.2007.96
M3 - Conference contribution
AN - SCOPUS:47749148980
SN - 0769527620
SN - 9780769527628
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 621
EP - 626
BT - Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Y2 - 6 January 2007 through 10 January 2007
ER -