Abstract
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates system-level floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC architecture with complete information of the floorplan. In comparison to an existing approach, our technique results in lower total power consumption and much lower link power consumption.
| Original language | English (US) |
|---|---|
| Title of host publication | CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis |
| Pages | 136-141 |
| Number of pages | 6 |
| DOIs | |
| State | Published - 2006 |
| Event | CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis - Seoul, Korea, Republic of Duration: Oct 22 2006 → Oct 25 2006 |
Other
| Other | CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis |
|---|---|
| Country | Korea, Republic of |
| City | Seoul |
| Period | 10/22/06 → 10/25/06 |
Fingerprint
Keywords
- Automated design
- Mesh topology
- Network-on-chip
ASJC Scopus subject areas
- Computer Networks and Communications
- Hardware and Architecture
- Software
Cite this
Layout aware design of mesh based NoC architectures. / Srinivasan, Krishnan; Chatha, Karam S.
CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis. 2006. p. 136-141.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Layout aware design of mesh based NoC architectures
AU - Srinivasan, Krishnan
AU - Chatha, Karam S.
PY - 2006
Y1 - 2006
N2 - Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates system-level floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC architecture with complete information of the floorplan. In comparison to an existing approach, our technique results in lower total power consumption and much lower link power consumption.
AB - Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates system-level floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC architecture with complete information of the floorplan. In comparison to an existing approach, our technique results in lower total power consumption and much lower link power consumption.
KW - Automated design
KW - Mesh topology
KW - Network-on-chip
UR - http://www.scopus.com/inward/record.url?scp=34547192739&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34547192739&partnerID=8YFLogxK
U2 - 10.1145/1176254.1176288
DO - 10.1145/1176254.1176288
M3 - Conference contribution
AN - SCOPUS:34547192739
SN - 1595933700
SN - 9781595933706
SP - 136
EP - 141
BT - CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis
ER -