Layout aware design of mesh based NoC architectures

Krishnan Srinivasan, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates system-level floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC architecture with complete information of the floorplan. In comparison to an existing approach, our technique results in lower total power consumption and much lower link power consumption.

Original languageEnglish (US)
Title of host publicationCODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis
Pages136-141
Number of pages6
DOIs
StatePublished - 2006
EventCODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis - Seoul, Korea, Republic of
Duration: Oct 22 2006Oct 25 2006

Other

OtherCODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis
CountryKorea, Republic of
CitySeoul
Period10/22/0610/25/06

Fingerprint

Electric power utilization
Routers
Topology
Network-on-chip
Processing

Keywords

  • Automated design
  • Mesh topology
  • Network-on-chip

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

Cite this

Srinivasan, K., & Chatha, K. S. (2006). Layout aware design of mesh based NoC architectures. In CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis (pp. 136-141) https://doi.org/10.1145/1176254.1176288

Layout aware design of mesh based NoC architectures. / Srinivasan, Krishnan; Chatha, Karam S.

CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis. 2006. p. 136-141.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Srinivasan, K & Chatha, KS 2006, Layout aware design of mesh based NoC architectures. in CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis. pp. 136-141, CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis, Seoul, Korea, Republic of, 10/22/06. https://doi.org/10.1145/1176254.1176288
Srinivasan K, Chatha KS. Layout aware design of mesh based NoC architectures. In CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis. 2006. p. 136-141 https://doi.org/10.1145/1176254.1176288
Srinivasan, Krishnan ; Chatha, Karam S. / Layout aware design of mesh based NoC architectures. CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis. 2006. pp. 136-141
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