Abstract
Digital circuits require positive static noise margin for correct operation. An 7nalytical model of amorphous silicon digital circuit raise margin is described here. The model is verified with experimental measurements. The circuit aging effects that increase threshold voltage of a-Si:H TFTs over time with electrical stress are used to determine the circuit lifetime under continuous operation.
Original language | English (US) |
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Title of host publication | Digest of Technical Papers - SID International Symposium |
Pages | 270-273 |
Number of pages | 4 |
Volume | 37 |
Edition | 1 |
State | Published - 2006 |
Event | 44th International Symposium, Seminar, and Exhibition, SID 2006 - San Francisco, CA, United States Duration: Jun 4 2006 → Jun 9 2006 |
Other
Other | 44th International Symposium, Seminar, and Exhibition, SID 2006 |
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Country/Territory | United States |
City | San Francisco, CA |
Period | 6/4/06 → 6/9/06 |
ASJC Scopus subject areas
- General Engineering