Late-news poster: An analytical lifetime model for digital a-Si:H circuits

Sameer Venugopal Zi Li, Rahul Shringarpure, David Allee, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Digital circuits require positive static noise margin for correct operation. An 7nalytical model of amorphous silicon digital circuit raise margin is described here. The model is verified with experimental measurements. The circuit aging effects that increase threshold voltage of a-Si:H TFTs over time with electrical stress are used to determine the circuit lifetime under continuous operation.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - SID International Symposium
Pages270-273
Number of pages4
Volume37
Edition1
StatePublished - 2006
Event44th International Symposium, Seminar, and Exhibition, SID 2006 - San Francisco, CA, United States
Duration: Jun 4 2006Jun 9 2006

Other

Other44th International Symposium, Seminar, and Exhibition, SID 2006
CountryUnited States
CitySan Francisco, CA
Period6/4/066/9/06

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Zi Li, S. V., Shringarpure, R., Allee, D., & Clark, L. T. (2006). Late-news poster: An analytical lifetime model for digital a-Si:H circuits. In Digest of Technical Papers - SID International Symposium (1 ed., Vol. 37, pp. 270-273)