Large-scale broadband parasitic extraction for fast layout verification of 3D RF and mixed-signal on-chip structures

In this paper, a methodology for efficient parasitic extraction and verification flow for the large scale fragments of the RF and mixed-signal ASIC is presented. The usage of a multi-plane precorrected-FFT (PFFT) computational engine enables the full-wave electromagnetic (EM) simulation of the critical nets. The broadband capability of the EM solver is provided through the loop-tree/charge implementation of the PFFT algorithm allowing for numerically efficient and robust full-wave modeling from DC to microwaves. The EM verification flow is integrated seamlessly within the Cadence environment. Thus, the network parameters for the distributed 3D integrated passives obtained with electromagnetic accuracy can be back-annotated to the corresponding schematic for subsequent non-linear circuit simulation of the entire device. The capability and the accuracy of the proposed methodology is demonstrated through EM simulation results for an individual on-chip spiral inductor as well as the Gilbert cell mixer.