TY - JOUR
T1 - Large-scale broad-band parasitic extraction for fast layout verification of 3-D RF and mixed-signal on-chip structures
AU - Ling, Feng
AU - Okhmatovski, Vladimir I.
AU - Harris, Warren
AU - McCracken, Stephen
AU - Dengi, Aykut
N1 - Funding Information:
Manuscript received April 21, 2004; revised July 3, 2004. This work was supported by the Defense Advanced Research Projects Agency NeoCAD Program under Grant TIA F33615-01-2-1970 and managed by the Sensors Directorate of the Air Force Research Laboratory, U.S. Air Force, Wright-Patterson AFB, OH.
PY - 2005/1
Y1 - 2005/1
N2 - In this paper, a methodology for efficient parasitic extraction and verification flow for RF and mixed-signal integrated-circuit designs is presented. The implementation of a multiplane precorrected fast Fourier transform (PFFT) computational engine enables the full-wave electromagnetic (EM) simulation of interconnects and passive components. The PFFT algorithm is implemented on a set of two-dimensional fast Fourier transform grids associated with the current sheets corresponding to the conductor loss models. This leads to the full-wave modeling of silicon embedded three-dimensional circuits within the two-and-one-half-dimensional computational framework yielding the O(N log N) computational complexity and O(N) memory requirements of the algorithm. The broad-band capability of the EM solver is provided through the loop-tree/charge implementation of the PFFT algorithm allowing for robust full-wave modeling from dc to microwaves. The EM verification flow is integrated seamlessly within the Cadence environment allowing for non-linear circuit simulation of the entire device. The capability and accuracy of the proposed methodology is demonstrated through EM simulation results for an individual on-chip spiral inductor, as well as a low-noise amplifier.
AB - In this paper, a methodology for efficient parasitic extraction and verification flow for RF and mixed-signal integrated-circuit designs is presented. The implementation of a multiplane precorrected fast Fourier transform (PFFT) computational engine enables the full-wave electromagnetic (EM) simulation of interconnects and passive components. The PFFT algorithm is implemented on a set of two-dimensional fast Fourier transform grids associated with the current sheets corresponding to the conductor loss models. This leads to the full-wave modeling of silicon embedded three-dimensional circuits within the two-and-one-half-dimensional computational framework yielding the O(N log N) computational complexity and O(N) memory requirements of the algorithm. The broad-band capability of the EM solver is provided through the loop-tree/charge implementation of the PFFT algorithm allowing for robust full-wave modeling from dc to microwaves. The EM verification flow is integrated seamlessly within the Cadence environment allowing for non-linear circuit simulation of the entire device. The capability and accuracy of the proposed methodology is demonstrated through EM simulation results for an individual on-chip spiral inductor, as well as a low-noise amplifier.
KW - Electromagnetic (EM) solver
KW - Fast algorithm
KW - Method of moments (MoM)
KW - Multiplane precorrected fast fourier transform (PFFT)
KW - Parasitic extraction
KW - Rf integrated circuit (RFIC)
KW - Spiral inductor
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U2 - 10.1109/TMTT.2004.839907
DO - 10.1109/TMTT.2004.839907
M3 - Article
AN - SCOPUS:12344312510
SN - 0018-9480
VL - 53
SP - 264
EP - 272
JO - IEEE Transactions on Microwave Theory and Techniques
JF - IEEE Transactions on Microwave Theory and Techniques
IS - 1
ER -