Large-scale broad-band parasitic extraction for fast layout verification of 3-D RF and mixed-signal on-chip structures

Feng Ling, Vladimir I. Okhmatovski, Warren Harris, Stephen McCracken, Enis Dengi

Research output: Contribution to journalArticle

39 Citations (Scopus)

Abstract

In this paper, a methodology for efficient parasitic extraction and verification flow for RF and mixed-signal integrated-circuit designs is presented. The implementation of a multiplane precorrected fast Fourier transform (PFFT) computational engine enables the full-wave electromagnetic (EM) simulation of interconnects and passive components. The PFFT algorithm is implemented on a set of two-dimensional fast Fourier transform grids associated with the current sheets corresponding to the conductor loss models. This leads to the full-wave modeling of silicon embedded three-dimensional circuits within the two-and-one-half-dimensional computational framework yielding the O(N log N) computational complexity and O(N) memory requirements of the algorithm. The broad-band capability of the EM solver is provided through the loop-tree/charge implementation of the PFFT algorithm allowing for robust full-wave modeling from dc to microwaves. The EM verification flow is integrated seamlessly within the Cadence environment allowing for non-linear circuit simulation of the entire device. The capability and accuracy of the proposed methodology is demonstrated through EM simulation results for an individual on-chip spiral inductor, as well as a low-noise amplifier.

Original languageEnglish (US)
Pages (from-to)264-272
Number of pages9
JournalIEEE Transactions on Microwave Theory and Techniques
Volume53
Issue number1
DOIs
StatePublished - Jan 1 2005
Externally publishedYes

Fingerprint

Fast Fourier transforms
layouts
chips
electromagnetism
broadband
methodology
simulation
current sheets
inductors
low noise
integrated circuits
engines
Low noise amplifiers
Circuit simulation
electromagnetic radiation
conductors
amplifiers
grids
Electromagnetic waves
microwaves

Keywords

  • Electromagnetic (EM) solver
  • Fast algorithm
  • Method of moments (MoM)
  • Multiplane precorrected fast fourier transform (PFFT)
  • Parasitic extraction
  • Rf integrated circuit (RFIC)
  • Spiral inductor

ASJC Scopus subject areas

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Large-scale broad-band parasitic extraction for fast layout verification of 3-D RF and mixed-signal on-chip structures. / Ling, Feng; Okhmatovski, Vladimir I.; Harris, Warren; McCracken, Stephen; Dengi, Enis.

In: IEEE Transactions on Microwave Theory and Techniques, Vol. 53, No. 1, 01.01.2005, p. 264-272.

Research output: Contribution to journalArticle

Ling, Feng ; Okhmatovski, Vladimir I. ; Harris, Warren ; McCracken, Stephen ; Dengi, Enis. / Large-scale broad-band parasitic extraction for fast layout verification of 3-D RF and mixed-signal on-chip structures. In: IEEE Transactions on Microwave Theory and Techniques. 2005 ; Vol. 53, No. 1. pp. 264-272.
@article{c24d41c88cf5474ea5bdd4b3c387e0e3,
title = "Large-scale broad-band parasitic extraction for fast layout verification of 3-D RF and mixed-signal on-chip structures",
abstract = "In this paper, a methodology for efficient parasitic extraction and verification flow for RF and mixed-signal integrated-circuit designs is presented. The implementation of a multiplane precorrected fast Fourier transform (PFFT) computational engine enables the full-wave electromagnetic (EM) simulation of interconnects and passive components. The PFFT algorithm is implemented on a set of two-dimensional fast Fourier transform grids associated with the current sheets corresponding to the conductor loss models. This leads to the full-wave modeling of silicon embedded three-dimensional circuits within the two-and-one-half-dimensional computational framework yielding the O(N log N) computational complexity and O(N) memory requirements of the algorithm. The broad-band capability of the EM solver is provided through the loop-tree/charge implementation of the PFFT algorithm allowing for robust full-wave modeling from dc to microwaves. The EM verification flow is integrated seamlessly within the Cadence environment allowing for non-linear circuit simulation of the entire device. The capability and accuracy of the proposed methodology is demonstrated through EM simulation results for an individual on-chip spiral inductor, as well as a low-noise amplifier.",
keywords = "Electromagnetic (EM) solver, Fast algorithm, Method of moments (MoM), Multiplane precorrected fast fourier transform (PFFT), Parasitic extraction, Rf integrated circuit (RFIC), Spiral inductor",
author = "Feng Ling and Okhmatovski, {Vladimir I.} and Warren Harris and Stephen McCracken and Enis Dengi",
year = "2005",
month = "1",
day = "1",
doi = "10.1109/TMTT.2004.839907",
language = "English (US)",
volume = "53",
pages = "264--272",
journal = "IEEE Transactions on Microwave Theory and Techniques",
issn = "0018-9480",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - Large-scale broad-band parasitic extraction for fast layout verification of 3-D RF and mixed-signal on-chip structures

AU - Ling, Feng

AU - Okhmatovski, Vladimir I.

AU - Harris, Warren

AU - McCracken, Stephen

AU - Dengi, Enis

PY - 2005/1/1

Y1 - 2005/1/1

N2 - In this paper, a methodology for efficient parasitic extraction and verification flow for RF and mixed-signal integrated-circuit designs is presented. The implementation of a multiplane precorrected fast Fourier transform (PFFT) computational engine enables the full-wave electromagnetic (EM) simulation of interconnects and passive components. The PFFT algorithm is implemented on a set of two-dimensional fast Fourier transform grids associated with the current sheets corresponding to the conductor loss models. This leads to the full-wave modeling of silicon embedded three-dimensional circuits within the two-and-one-half-dimensional computational framework yielding the O(N log N) computational complexity and O(N) memory requirements of the algorithm. The broad-band capability of the EM solver is provided through the loop-tree/charge implementation of the PFFT algorithm allowing for robust full-wave modeling from dc to microwaves. The EM verification flow is integrated seamlessly within the Cadence environment allowing for non-linear circuit simulation of the entire device. The capability and accuracy of the proposed methodology is demonstrated through EM simulation results for an individual on-chip spiral inductor, as well as a low-noise amplifier.

AB - In this paper, a methodology for efficient parasitic extraction and verification flow for RF and mixed-signal integrated-circuit designs is presented. The implementation of a multiplane precorrected fast Fourier transform (PFFT) computational engine enables the full-wave electromagnetic (EM) simulation of interconnects and passive components. The PFFT algorithm is implemented on a set of two-dimensional fast Fourier transform grids associated with the current sheets corresponding to the conductor loss models. This leads to the full-wave modeling of silicon embedded three-dimensional circuits within the two-and-one-half-dimensional computational framework yielding the O(N log N) computational complexity and O(N) memory requirements of the algorithm. The broad-band capability of the EM solver is provided through the loop-tree/charge implementation of the PFFT algorithm allowing for robust full-wave modeling from dc to microwaves. The EM verification flow is integrated seamlessly within the Cadence environment allowing for non-linear circuit simulation of the entire device. The capability and accuracy of the proposed methodology is demonstrated through EM simulation results for an individual on-chip spiral inductor, as well as a low-noise amplifier.

KW - Electromagnetic (EM) solver

KW - Fast algorithm

KW - Method of moments (MoM)

KW - Multiplane precorrected fast fourier transform (PFFT)

KW - Parasitic extraction

KW - Rf integrated circuit (RFIC)

KW - Spiral inductor

UR - http://www.scopus.com/inward/record.url?scp=12344312510&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=12344312510&partnerID=8YFLogxK

U2 - 10.1109/TMTT.2004.839907

DO - 10.1109/TMTT.2004.839907

M3 - Article

VL - 53

SP - 264

EP - 272

JO - IEEE Transactions on Microwave Theory and Techniques

JF - IEEE Transactions on Microwave Theory and Techniques

SN - 0018-9480

IS - 1

ER -