Abstract

Parameter variations in deep sub-micron integrated circuits cause chip characteristics to deviate during semiconductor fabrication process. These variations are dominant in memory systems such as caches and the delay spread due to process variation impacts the performance of a cache based system significantly. In this paper, we propose two schemes to reduce the performance impact of variations in caches: i) Latency-Aware Least Recently Used (LA-LRU) replacement policy which ensures that cache blocks that are affected by process variation are accessed less frequently, and ii) Block Rearrangement scheme that distributes cache blocks with high latencies to all sets uniformly. We implemented our schemes on the Wattch SimpleScalar toolset for Xscale, PowerPC and Alpha21264-like processor configurations. Our experiments on SPEC 2000 benchmarks show that our scheme improves the average memory access time of caches by 11% to 22%, almost eliminating any performance degradation due to variations. We also synthesized the LA-LRU logic, to find out that we can obtain this benefit at negligible increase in the power consumption of the cache.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
Pages298-303
Number of pages6
DOIs
StatePublished - 2011
Event24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems - Chennai, India
Duration: Jan 2 2011Jan 7 2011

Other

Other24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems
CountryIndia
CityChennai
Period1/2/111/7/11

Fingerprint

Data storage equipment
Integrated circuits
Electric power utilization
Semiconductor materials
Fabrication
Degradation
Experiments

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Jain, A., Shrivastava, A., & Chakrabarti, C. (2011). LA-LRU: A latency-aware replacement policy for variation tolerant caches. In Proceedings of the IEEE International Conference on VLSI Design (pp. 298-303). [5718818] https://doi.org/10.1109/VLSID.2011.24

LA-LRU : A latency-aware replacement policy for variation tolerant caches. / Jain, Aarul; Shrivastava, Aviral; Chakrabarti, Chaitali.

Proceedings of the IEEE International Conference on VLSI Design. 2011. p. 298-303 5718818.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jain, A, Shrivastava, A & Chakrabarti, C 2011, LA-LRU: A latency-aware replacement policy for variation tolerant caches. in Proceedings of the IEEE International Conference on VLSI Design., 5718818, pp. 298-303, 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems, Chennai, India, 1/2/11. https://doi.org/10.1109/VLSID.2011.24
Jain A, Shrivastava A, Chakrabarti C. LA-LRU: A latency-aware replacement policy for variation tolerant caches. In Proceedings of the IEEE International Conference on VLSI Design. 2011. p. 298-303. 5718818 https://doi.org/10.1109/VLSID.2011.24
Jain, Aarul ; Shrivastava, Aviral ; Chakrabarti, Chaitali. / LA-LRU : A latency-aware replacement policy for variation tolerant caches. Proceedings of the IEEE International Conference on VLSI Design. 2011. pp. 298-303
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