Knowledge- And simulation-based synthesis of area-efficient passive loop filter incremental zoom-ADC for built-in self-test applications

O. Erol, Sule Ozev

Research output: Contribution to journalArticle

Abstract

We propose a fully differential, synthesizable zoom-ADC architecture with a passive loop filter for low-frequency Built-In Self-Test (BIST) applications, along with a synthesis tool that can target various design specifications. We present the detailed ADC architecture and a step-by-step process for designing the zoom-ADC. The design flow does not rely on the extensive knowledge of an experienced ADC designer. Two ADCs have been synthesized with different performance requirements in the 65nm CMOS process. The first ADC achieves a 90.4dB Signal-to-Noise Ratio (SNR) in 512μs measurement time and consumes 17μW power. The second design achieves a 78.2dB SNR in 31.25μs measurement time and consumes 63μW power.

Original languageEnglish (US)
Article number3
JournalACM Transactions on Design Automation of Electronic Systems
Volume24
Issue number1
DOIs
StatePublished - Jan 1 2019

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Built-in self test
Time measurement
Signal to noise ratio
Specifications

Keywords

  • Design automation
  • Incremental zooming ADC
  • Passive delta sigma modulators

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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