KANSYS: A CAD tool for analog circuit synthesis

Sandeep Gupta, M. M. Hasan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

A CAD tool for the synthesis of analog circuits has been developed. The approach adopted is top down, knowledge intensive hierarchical design. A flattened view of the design is not however lost sight of and design knowledge over various levels of hierarchy is also used to achieve desirable performance. Practical sized transistor circuit designs are synthesized for CMOS OPAMPS and some of the functional circuits from performance and process specifications.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
Place of PublicationLos Alamitos, CA, United States
PublisherIEEE
Pages333-334
Number of pages2
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 9th International Conference on VLSI Design - Bangalore, India
Duration: Jan 3 1996Jan 6 1996

Other

OtherProceedings of the 1996 9th International Conference on VLSI Design
CityBangalore, India
Period1/3/961/6/96

Fingerprint

Analog circuits
Computer aided design
Networks (circuits)
Transistors
Specifications

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Gupta, S., & Hasan, M. M. (1996). KANSYS: A CAD tool for analog circuit synthesis. In Proceedings of the IEEE International Conference on VLSI Design (pp. 333-334). Los Alamitos, CA, United States: IEEE.

KANSYS : A CAD tool for analog circuit synthesis. / Gupta, Sandeep; Hasan, M. M.

Proceedings of the IEEE International Conference on VLSI Design. Los Alamitos, CA, United States : IEEE, 1996. p. 333-334.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gupta, S & Hasan, MM 1996, KANSYS: A CAD tool for analog circuit synthesis. in Proceedings of the IEEE International Conference on VLSI Design. IEEE, Los Alamitos, CA, United States, pp. 333-334, Proceedings of the 1996 9th International Conference on VLSI Design, Bangalore, India, 1/3/96.
Gupta S, Hasan MM. KANSYS: A CAD tool for analog circuit synthesis. In Proceedings of the IEEE International Conference on VLSI Design. Los Alamitos, CA, United States: IEEE. 1996. p. 333-334
Gupta, Sandeep ; Hasan, M. M. / KANSYS : A CAD tool for analog circuit synthesis. Proceedings of the IEEE International Conference on VLSI Design. Los Alamitos, CA, United States : IEEE, 1996. pp. 333-334
@inproceedings{6bc5521dcb25449d8603391621b9c7fa,
title = "KANSYS: A CAD tool for analog circuit synthesis",
abstract = "A CAD tool for the synthesis of analog circuits has been developed. The approach adopted is top down, knowledge intensive hierarchical design. A flattened view of the design is not however lost sight of and design knowledge over various levels of hierarchy is also used to achieve desirable performance. Practical sized transistor circuit designs are synthesized for CMOS OPAMPS and some of the functional circuits from performance and process specifications.",
author = "Sandeep Gupta and Hasan, {M. M.}",
year = "1996",
language = "English (US)",
pages = "333--334",
booktitle = "Proceedings of the IEEE International Conference on VLSI Design",
publisher = "IEEE",

}

TY - GEN

T1 - KANSYS

T2 - A CAD tool for analog circuit synthesis

AU - Gupta, Sandeep

AU - Hasan, M. M.

PY - 1996

Y1 - 1996

N2 - A CAD tool for the synthesis of analog circuits has been developed. The approach adopted is top down, knowledge intensive hierarchical design. A flattened view of the design is not however lost sight of and design knowledge over various levels of hierarchy is also used to achieve desirable performance. Practical sized transistor circuit designs are synthesized for CMOS OPAMPS and some of the functional circuits from performance and process specifications.

AB - A CAD tool for the synthesis of analog circuits has been developed. The approach adopted is top down, knowledge intensive hierarchical design. A flattened view of the design is not however lost sight of and design knowledge over various levels of hierarchy is also used to achieve desirable performance. Practical sized transistor circuit designs are synthesized for CMOS OPAMPS and some of the functional circuits from performance and process specifications.

UR - http://www.scopus.com/inward/record.url?scp=0029697702&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029697702&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029697702

SP - 333

EP - 334

BT - Proceedings of the IEEE International Conference on VLSI Design

PB - IEEE

CY - Los Alamitos, CA, United States

ER -