Abstract
A CAD tool for the synthesis of analog circuits has been developed. The approach adopted is top down, knowledge intensive hierarchical design. A flattened view of the design is not however lost sight of and design knowledge over various levels of hierarchy is also used to achieve desirable performance. Practical sized transistor circuit designs are synthesized for CMOS OPAMPS and some of the functional circuits from performance and process specifications.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the IEEE International Conference on VLSI Design |
| Place of Publication | Los Alamitos, CA, United States |
| Publisher | IEEE |
| Pages | 333-334 |
| Number of pages | 2 |
| State | Published - 1996 |
| Externally published | Yes |
| Event | Proceedings of the 1996 9th International Conference on VLSI Design - Bangalore, India Duration: Jan 3 1996 → Jan 6 1996 |
Other
| Other | Proceedings of the 1996 9th International Conference on VLSI Design |
|---|---|
| City | Bangalore, India |
| Period | 1/3/96 → 1/6/96 |
ASJC Scopus subject areas
- General Engineering