TY - GEN
T1 - K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM
AU - Saikia, Jyotishman
AU - Yin, Shihui
AU - Jiang, Zhewei
AU - Seok, Mingoo
AU - Seo, Jae Sun
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - The k-nearest neighbor (kNN) is one of the most popular algorithms in machine learning owing to its simplicity, versatility, and implementation viability without any assumptions about the data. However, for large-scale data, it incurs a large amount of memory access and computational complexity, resulting in long latency and high power consumption. In this paper, we present a kNN hardware accelerator in 65nm CMOS. This accelerator combines in-memory computing SRAM that is recently developed for binarized deep neural networks and digital hardware that performs top-k sorting. We designed and simulated the kNN accelerator, which performs up to 17.9 million query vectors per second while consuming 11.8 mW, demonstrating >4.8X energy improvement over prior works.
AB - The k-nearest neighbor (kNN) is one of the most popular algorithms in machine learning owing to its simplicity, versatility, and implementation viability without any assumptions about the data. However, for large-scale data, it incurs a large amount of memory access and computational complexity, resulting in long latency and high power consumption. In this paper, we present a kNN hardware accelerator in 65nm CMOS. This accelerator combines in-memory computing SRAM that is recently developed for binarized deep neural networks and digital hardware that performs top-k sorting. We designed and simulated the kNN accelerator, which performs up to 17.9 million query vectors per second while consuming 11.8 mW, demonstrating >4.8X energy improvement over prior works.
KW - content addressable memory
KW - hardware accelerator
KW - in-memory computing
KW - k-nearest neighbor
UR - http://www.scopus.com/inward/record.url?scp=85072652982&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85072652982&partnerID=8YFLogxK
U2 - 10.1109/ISLPED.2019.8824822
DO - 10.1109/ISLPED.2019.8824822
M3 - Conference contribution
AN - SCOPUS:85072652982
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
BT - International Symposium on Low Power Electronics and Design, ISLPED 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019
Y2 - 29 July 2019 through 31 July 2019
ER -