TY - GEN
T1 - Janus
T2 - 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
AU - Hosseinzadeh, Hossein
AU - Isakov, Mihailo
AU - Darabi, Mostafa
AU - Patooghy, Ahmad
AU - Kinsy, Michel A.
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/27
Y1 - 2017/9/27
N2 - Side channel attacks are a major class of attacks to crypto-systems. Attackers collect and analyze timing behavior, I/O data, or power consumption in these systems to undermine their effectiveness in protecting sensitive information. In this work, we propose a new cache architecture, called Janus, to enable crypto-systems to introduce randomization and uncertainty in their runtime timing behavior and power utilization profile. In the proposed cache architecture, each data block is equipped with an on-off flag to enable/disable the data block. The Janus architecture has two special instructions in its instruction set to support the on-off flag. Beside the analytical evaluation of the proposed cache architecture, we deploy it in an ARM-7 processor core to study its feasibility and practicality. Results show a significant variation in the timing behavior across all the benchmarks. The new secure processor architecture has minimal hardware overhead and significant improvement in protecting against power analysis and timing behavior attacks.
AB - Side channel attacks are a major class of attacks to crypto-systems. Attackers collect and analyze timing behavior, I/O data, or power consumption in these systems to undermine their effectiveness in protecting sensitive information. In this work, we propose a new cache architecture, called Janus, to enable crypto-systems to introduce randomization and uncertainty in their runtime timing behavior and power utilization profile. In the proposed cache architecture, each data block is equipped with an on-off flag to enable/disable the data block. The Janus architecture has two special instructions in its instruction set to support the on-off flag. Beside the analytical evaluation of the proposed cache architecture, we deploy it in an ARM-7 processor core to study its feasibility and practicality. Results show a significant variation in the timing behavior across all the benchmarks. The new secure processor architecture has minimal hardware overhead and significant improvement in protecting against power analysis and timing behavior attacks.
UR - http://www.scopus.com/inward/record.url?scp=85034057265&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85034057265&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2017.8053051
DO - 10.1109/MWSCAS.2017.8053051
M3 - Conference contribution
AN - SCOPUS:85034057265
T3 - Midwest Symposium on Circuits and Systems
SP - 827
EP - 830
BT - 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 6 August 2017 through 9 August 2017
ER -