TY - JOUR
T1 - "It's a small world after all"
T2 - NoC performance optimization via long-range link insertion
AU - Ogras, Umit Y.
AU - Marculescu, Radu
N1 - Funding Information:
Manuscript received July 1, 2005; revised January 16, 2006. This work was supported by the Marco Gigascale Systems Research Center (GSRC). The authors are with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213-3890 USA (e-mail: uogras@ece.cmu.edu; radum@ece.cmu.edu). Digital Object Identifier 10.1109/TVLSI.2006.878263
PY - 2006/7
Y1 - 2006/7
N2 - Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.
AB - Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.
KW - Design automation
KW - Multiprocessor system-on-chip (MP-SoC)
KW - Network-on-chip (NoC)
KW - Performance analysis
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U2 - 10.1109/TVLSI.2006.878263
DO - 10.1109/TVLSI.2006.878263
M3 - Article
AN - SCOPUS:33746930901
SN - 1063-8210
VL - 14
SP - 693
EP - 706
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 7
M1 - 1661619
ER -