Iterative algorithm for partitioning and scheduling of area constrained HW-SW systems

Karam S. Chatha, Ranga Vemuri

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Scopus citations

Abstract

This paper presents a technique for integrated partitioning and scheduling of hardware-software systems. The tool takes a task graph and area constraint as input and obtains a mapping and schedule such that the execution time is minimized. The algorithm differs from other approaches which either obtain the mapping during the partitioning stage or the scheduling stage. We use an iterative approach where the partitioner assigns the mapping of only some of the tasks and the remaining tasks are assigned by the scheduler with an objective of minimizing the execution time. The technique takes both the time and area overheads due to inter-processor and intra-processor communication into output. The effectiveness of the approach is demonstrated by the experimental results.

Original languageEnglish (US)
Title of host publicationProceedings of the International Workshop on Rapid System Prototyping
PublisherIEEE
Pages134-139
Number of pages6
StatePublished - 1999
Externally publishedYes
EventProceedings of the 1999 10th IEEE International Workshop on Rapid System Prototyping (RSP'99) - Clearwater, FL, USA
Duration: Jun 16 1999Jun 18 1999

Other

OtherProceedings of the 1999 10th IEEE International Workshop on Rapid System Prototyping (RSP'99)
CityClearwater, FL, USA
Period6/16/996/18/99

ASJC Scopus subject areas

  • Software
  • Safety, Risk, Reliability and Quality

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    Chatha, K. S., & Vemuri, R. (1999). Iterative algorithm for partitioning and scheduling of area constrained HW-SW systems. In Proceedings of the International Workshop on Rapid System Prototyping (pp. 134-139). IEEE.