Abstract
This paper presents a technique for integrated partitioning and scheduling of hardware-software systems. The tool takes a task graph and area constraint as input and obtains a mapping and schedule such that the execution time is minimized. The algorithm differs from other approaches which either obtain the mapping during the partitioning stage or the scheduling stage. We use an iterative approach where the partitioner assigns the mapping of only some of the tasks and the remaining tasks are assigned by the scheduler with an objective of minimizing the execution time. The technique takes both the time and area overheads due to inter-processor and intra-processor communication into output. The effectiveness of the approach is demonstrated by the experimental results.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the International Workshop on Rapid System Prototyping |
| Publisher | IEEE |
| Pages | 134-139 |
| Number of pages | 6 |
| State | Published - 1999 |
| Externally published | Yes |
| Event | Proceedings of the 1999 10th IEEE International Workshop on Rapid System Prototyping (RSP'99) - Clearwater, FL, USA Duration: Jun 16 1999 → Jun 18 1999 |
Other
| Other | Proceedings of the 1999 10th IEEE International Workshop on Rapid System Prototyping (RSP'99) |
|---|---|
| City | Clearwater, FL, USA |
| Period | 6/16/99 → 6/18/99 |
ASJC Scopus subject areas
- Software
- Safety, Risk, Reliability and Quality