ISIS: A genetic algorithm based technique for custom on-chip interconnection network synthesis

Krishnan Srinivasan, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

40 Scopus citations

Abstract

On-chip packet switched interconnection networks (or Network-on-chip (NoC)) have been proposed as a solution to the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents ISIS, a novel genetic algorithm (GA) based technique for custom NoC synthesis that optimizes both the power consumption and area of the design subject to the performance constraints, and generates a custom NoC topology and mapping of the communication traces on the architecture. ISIS solves a multi-objective optimization problem by minimizing a cost function expressed as a linear combination of the cost incurred due to power consumption and area. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions.

Original languageEnglish (US)
Title of host publicationProceedings of the 18th International Conference on VLSI Design
Pages623-628
Number of pages6
DOIs
StatePublished - Dec 1 2005
Event18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India
Duration: Jan 3 2005Jan 7 2005

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
CountryIndia
CityKolkata
Period1/3/051/7/05

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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