TY - GEN
T1 - ISIS
T2 - 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
AU - Srinivasan, Krishnan
AU - Chatha, Karam S.
PY - 2005/12/1
Y1 - 2005/12/1
N2 - On-chip packet switched interconnection networks (or Network-on-chip (NoC)) have been proposed as a solution to the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents ISIS, a novel genetic algorithm (GA) based technique for custom NoC synthesis that optimizes both the power consumption and area of the design subject to the performance constraints, and generates a custom NoC topology and mapping of the communication traces on the architecture. ISIS solves a multi-objective optimization problem by minimizing a cost function expressed as a linear combination of the cost incurred due to power consumption and area. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions.
AB - On-chip packet switched interconnection networks (or Network-on-chip (NoC)) have been proposed as a solution to the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents ISIS, a novel genetic algorithm (GA) based technique for custom NoC synthesis that optimizes both the power consumption and area of the design subject to the performance constraints, and generates a custom NoC topology and mapping of the communication traces on the architecture. ISIS solves a multi-objective optimization problem by minimizing a cost function expressed as a linear combination of the cost incurred due to power consumption and area. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions.
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U2 - 10.1109/ICVD.2005.113
DO - 10.1109/ICVD.2005.113
M3 - Conference contribution
AN - SCOPUS:27944442417
SN - 0769522645
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 623
EP - 628
BT - Proceedings of the 18th International Conference on VLSI Design
Y2 - 3 January 2005 through 7 January 2005
ER -