Abstract
On-chip packet switched interconnection networks (or Network-on-chip (NoC)) have been proposed as a solution to the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents ISIS, a novel genetic algorithm (GA) based technique for custom NoC synthesis that optimizes both the power consumption and area of the design subject to the performance constraints, and generates a custom NoC topology and mapping of the communication traces on the architecture. ISIS solves a multi-objective optimization problem by minimizing a cost function expressed as a linear combination of the cost incurred due to power consumption and area. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the IEEE International Conference on VLSI Design |
| Pages | 623-628 |
| Number of pages | 6 |
| DOIs | |
| State | Published - 2005 |
| Event | 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India Duration: Jan 3 2005 → Jan 7 2005 |
Other
| Other | 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems |
|---|---|
| Country | India |
| City | Kolkata |
| Period | 1/3/05 → 1/7/05 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
ISIS : A genetic algorithm based technique for custom on-chip interconnection network synthesis. / Srinivasan, Krishnan; Chatha, Karam S.
Proceedings of the IEEE International Conference on VLSI Design. 2005. p. 623-628.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - ISIS
T2 - A genetic algorithm based technique for custom on-chip interconnection network synthesis
AU - Srinivasan, Krishnan
AU - Chatha, Karam S.
PY - 2005
Y1 - 2005
N2 - On-chip packet switched interconnection networks (or Network-on-chip (NoC)) have been proposed as a solution to the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents ISIS, a novel genetic algorithm (GA) based technique for custom NoC synthesis that optimizes both the power consumption and area of the design subject to the performance constraints, and generates a custom NoC topology and mapping of the communication traces on the architecture. ISIS solves a multi-objective optimization problem by minimizing a cost function expressed as a linear combination of the cost incurred due to power consumption and area. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions.
AB - On-chip packet switched interconnection networks (or Network-on-chip (NoC)) have been proposed as a solution to the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents ISIS, a novel genetic algorithm (GA) based technique for custom NoC synthesis that optimizes both the power consumption and area of the design subject to the performance constraints, and generates a custom NoC topology and mapping of the communication traces on the architecture. ISIS solves a multi-objective optimization problem by minimizing a cost function expressed as a linear combination of the cost incurred due to power consumption and area. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions.
UR - http://www.scopus.com/inward/record.url?scp=27944442417&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=27944442417&partnerID=8YFLogxK
U2 - 10.1109/ICVD.2005.113
DO - 10.1109/ICVD.2005.113
M3 - Conference contribution
AN - SCOPUS:27944442417
SN - 0769522645
SP - 623
EP - 628
BT - Proceedings of the IEEE International Conference on VLSI Design
ER -