Investigation of power delay trade-offs on powerPC circuits

Logic and structural transformations to reduce power have been considered by a number of authors. [2, 3, 4, 5]. However, all the results presented so far have been based on models of power and estimation methods that may not be a accurate reflection of 'real world' constraints. The performance requirements of industrial designs often significantly restrict the applicability of the power reducing transformations. In this paper we present the results of investigations on the efficacy of a recently reported logic level power optimizing algorithm [5] on some commercial circuits, using customer supplied input waveforms. Based on a accurate delay model, the power consumption of the circuits is estimated using the commercial package called 'PowerMill'. The experimental results show that a maximum 21% average power and 27.7% peak power power reduction can be obtained with only 3% delay increase. Based on the experiments, we propose a general methodology for the practical application of the transformations for power optimization of CMOS logic circuits. Finally, a comparison between the experiments using random input waveforms and customer provided input waveforms is presented.