Investigation of defect generation and annihilation in IGZO TFTs during practical stress conditions: Illumination and electrical bias

This investigation elucidates the influence of standalone-bias stress and standalone-illumination stress, and their combinatory effect on indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). Each phenomenon associated with illumination (wavelengths of 410, 467, 532 and 632 nm) and bias (V_g = ±20 V; V_d = 0, 20 V) stresses is categorized individually. Wavelengths below 532 nm are responsible for ionized vacancy creation, carrier generation and interface state creation while only gate stresses of +20 V create excessive charge trap states. Failure conditions are identified as gate stresses of -20 V with 410 nm illumination. An improvement in the I_on/I_off ratio from 10⁶ to 10⁷ is due to increased charge contribution for on currents, and trapping of holes at the intermetallic dielectric near the source-channel junction in the off region. Upon stress removal TFTs exhibit incomplete recovery due to slow trapping of excited carriers from dielectric layers and inability created by the passivation layer to absorb oxygen for vacancy regeneration. The low-temperature fabrication and optimized post-fabrication anneal have created reduced defect and vacancy densities that make the IGZO TFTs more stable than the previous generation TFTs.