Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs

Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae sun Seo, Umit Y. Ogras, Yu Cao

Research output: Contribution to journalArticle

Original languageEnglish (US)
JournalIEEE Design and Test
DOIs
StateAccepted/In press - 2020

Keywords

  • Deep Neural Networks
  • In-Memory Computing
  • Interconnect
  • Network-on-Chip
  • Neural Network Accelerator
  • RRAM

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this