Integration of threshold logic gates with RRAM devices for energy efficient and robust operation

Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.

Original languageEnglish (US)
Title of host publicationProceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014
PublisherIEEE Computer Society
Pages39-44
Number of pages6
ISBN (Print)9781479963836
DOIs
StatePublished - 2014
Event2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014 - Paris, France
Duration: Jul 8 2014Jul 10 2014

Other

Other2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014
CountryFrance
CityParis
Period7/8/147/10/14

Fingerprint

Threshold logic
Logic gates
Networks (circuits)
Logic circuits
Electric potential
RRAM

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yang, J., Kulkarni, N., Yu, S., & Vrudhula, S. (2014). Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. In Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014 (pp. 39-44). [6880500] IEEE Computer Society. https://doi.org/10.1109/NANOARCH.2014.6880500

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. / Yang, Jinghua; Kulkarni, Niranjan; Yu, Shimeng; Vrudhula, Sarma.

Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014. IEEE Computer Society, 2014. p. 39-44 6880500.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yang, J, Kulkarni, N, Yu, S & Vrudhula, S 2014, Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. in Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014., 6880500, IEEE Computer Society, pp. 39-44, 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014, Paris, France, 7/8/14. https://doi.org/10.1109/NANOARCH.2014.6880500
Yang J, Kulkarni N, Yu S, Vrudhula S. Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. In Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014. IEEE Computer Society. 2014. p. 39-44. 6880500 https://doi.org/10.1109/NANOARCH.2014.6880500
Yang, Jinghua ; Kulkarni, Niranjan ; Yu, Shimeng ; Vrudhula, Sarma. / Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014. IEEE Computer Society, 2014. pp. 39-44
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