Integration of GaAs, Al-Ga-As and Related III-V and II-VI Compound Semiconductors with Si(100) via Lattice (stress/strained) Engineered SiGeSn Buffer Layers

John Kouvetakis (Inventor)

Research output: Patent

Abstract

Current commercial and defense electronics are based on Silicon (Si) while most RF and optical sources and detectors are based on III-V and II-VI semiconductors grown on non-Si substrates such as GaAs, InP, InAs, GaSb, and CdZnTe. This partitioning of the substrates poses major obstacles to device integration and restricts the choice of material systems that are candidates for bandgap engineering of future devices. To overcome these problems, this invention utilizes new methodologies for integration of III-V and II-VI compound semiconductors with Si via buffer layers based on novel Si-Ge-Sn alloys. In these methods, the lattice and the thermal expansion coefficient are simultaneously adjusted with composition to match those lattices and coefficients of the desired semiconductor. The buffer layers also provide a mechanism for suppression of threading defects in the overgrowth, resulting in low defect density and smooth surface morphology, which subsequently obviates post-growth chemical mechanical polishing treatments. The technology also provides low growth temperature (
Original languageEnglish (US)
StatePublished - Nov 30 2004

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title = "Integration of GaAs, Al-Ga-As and Related III-V and II-VI Compound Semiconductors with Si(100) via Lattice (stress/strained) Engineered SiGeSn Buffer Layers",
abstract = "Current commercial and defense electronics are based on Silicon (Si) while most RF and optical sources and detectors are based on III-V and II-VI semiconductors grown on non-Si substrates such as GaAs, InP, InAs, GaSb, and CdZnTe. This partitioning of the substrates poses major obstacles to device integration and restricts the choice of material systems that are candidates for bandgap engineering of future devices. To overcome these problems, this invention utilizes new methodologies for integration of III-V and II-VI compound semiconductors with Si via buffer layers based on novel Si-Ge-Sn alloys. In these methods, the lattice and the thermal expansion coefficient are simultaneously adjusted with composition to match those lattices and coefficients of the desired semiconductor. The buffer layers also provide a mechanism for suppression of threading defects in the overgrowth, resulting in low defect density and smooth surface morphology, which subsequently obviates post-growth chemical mechanical polishing treatments. The technology also provides low growth temperature (",
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year = "2004",
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language = "English (US)",
type = "Patent",

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N2 - Current commercial and defense electronics are based on Silicon (Si) while most RF and optical sources and detectors are based on III-V and II-VI semiconductors grown on non-Si substrates such as GaAs, InP, InAs, GaSb, and CdZnTe. This partitioning of the substrates poses major obstacles to device integration and restricts the choice of material systems that are candidates for bandgap engineering of future devices. To overcome these problems, this invention utilizes new methodologies for integration of III-V and II-VI compound semiconductors with Si via buffer layers based on novel Si-Ge-Sn alloys. In these methods, the lattice and the thermal expansion coefficient are simultaneously adjusted with composition to match those lattices and coefficients of the desired semiconductor. The buffer layers also provide a mechanism for suppression of threading defects in the overgrowth, resulting in low defect density and smooth surface morphology, which subsequently obviates post-growth chemical mechanical polishing treatments. The technology also provides low growth temperature (

AB - Current commercial and defense electronics are based on Silicon (Si) while most RF and optical sources and detectors are based on III-V and II-VI semiconductors grown on non-Si substrates such as GaAs, InP, InAs, GaSb, and CdZnTe. This partitioning of the substrates poses major obstacles to device integration and restricts the choice of material systems that are candidates for bandgap engineering of future devices. To overcome these problems, this invention utilizes new methodologies for integration of III-V and II-VI compound semiconductors with Si via buffer layers based on novel Si-Ge-Sn alloys. In these methods, the lattice and the thermal expansion coefficient are simultaneously adjusted with composition to match those lattices and coefficients of the desired semiconductor. The buffer layers also provide a mechanism for suppression of threading defects in the overgrowth, resulting in low defect density and smooth surface morphology, which subsequently obviates post-growth chemical mechanical polishing treatments. The technology also provides low growth temperature (

M3 - Patent

ER -