Integration issues in metallic source/drain nanoscale CMOS

M. Tao, M. Y. Ali, G. Song

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The performance of Schotky source'drain nanoscale CMOS is critically dependent on a low barrier between metal and Si. Low Schottky barriers have been recently realized with various metals on selenium or sulfur passivated Si(100) surface, with a ∼0-eV barrier height for electrons and a ∼0.17-eV barrier height for holes demonstrated. Several issues need to be addressed for integration of these low Schottky barriers into Schottky source/drain CMOS. This paper reports our recent results or low Schottky barriers on ntype and p-type Si(100) surface, thermal stability of these low Schottky barriers upon annealing, and self-aligned integration of these low-barrier metallic source/drain into nanoscale CMOS. Electrical characterization suggests that these low Schottky barriers are thermally stable to ∼400°C. A self-aligned fabrication process involving chemical mechanical polishing is proposed for these metallic source/drain CMOS devices.

Original languageEnglish (US)
Title of host publicationECS Transactions - 5th International Symposium on ULSI Process Integration
Pages253-263
Number of pages11
Edition6
DOIs
StatePublished - Dec 1 2007
Externally publishedYes
Event5th International Symposium on ULSI Process Integration - 212th ECS Meeting - Washington, DC, United States
Duration: Oct 7 2007Oct 12 2007

Publication series

NameECS Transactions
Number6
Volume11
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

Other5th International Symposium on ULSI Process Integration - 212th ECS Meeting
CountryUnited States
CityWashington, DC
Period10/7/0710/12/07

ASJC Scopus subject areas

  • Engineering(all)

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