Integration issues in metallic source/drain nanoscale CMOS

The performance of Schotky source'drain nanoscale CMOS is critically dependent on a low barrier between metal and Si. Low Schottky barriers have been recently realized with various metals on selenium or sulfur passivated Si(100) surface, with a ∼0-eV barrier height for electrons and a ∼0.17-eV barrier height for holes demonstrated. Several issues need to be addressed for integration of these low Schottky barriers into Schottky source/drain CMOS. This paper reports our recent results or low Schottky barriers on ntype and p-type Si(100) surface, thermal stability of these low Schottky barriers upon annealing, and self-aligned integration of these low-barrier metallic source/drain into nanoscale CMOS. Electrical characterization suggests that these low Schottky barriers are thermally stable to ∼400°C. A self-aligned fabrication process involving chemical mechanical polishing is proposed for these metallic source/drain CMOS devices.