Abstract

This study discusses thermally activated defects in the channel layer of indium zinc oxide (IZO) thin film transistors (TFTs) under electrical and thermal stress resembling practical stress scenarios. Operating temperatures of 20, 50, and 80 °C have been chosen to establish a relation between temperature and failure mechanism. With increasing stress period, acceptor- and donor-like traps contribute towards degrading drain current and subthreshold swing. Low temperature long hour anneal for 12, 24, 36, 48 and 60 hr at 150 °C are performed on the TFTs post fabrication to cure the defects formed during fabrication. Structures treated for 48 hr demonstrate high stability under extended kinetic stresses, maintaining a high transistor Ion/Ioff ratio of ∼ 108. A physicallybased mathematical model discusses the reduction in the density of acceptor-like trap states by 50 % for TFTs treated for 12 hrs, and to insignificant numbers for TFTs treated for 48 hr.

Original languageEnglish (US)
Title of host publicationThin Film Transistors 11, TFT 2012
Pages161-166
Number of pages6
Edition8
DOIs
StatePublished - Dec 1 2012
Event11th Symposium on Thin Film Transistor Technologies, TFT 2012 - PRiME 2012 - Honolulu, HI, United States
Duration: Oct 8 2012Oct 10 2012

Publication series

NameECS Transactions
Number8
Volume50
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

Other11th Symposium on Thin Film Transistor Technologies, TFT 2012 - PRiME 2012
CountryUnited States
CityHonolulu, HI
Period10/8/1210/10/12

ASJC Scopus subject areas

  • Engineering(all)

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    Vemuri, R. N. P., & Alford, T. (2012). Influence of thermal stress and kinetic bias stress on the electrical performance of mixed oxide thin film transistors. In Thin Film Transistors 11, TFT 2012 (8 ed., pp. 161-166). (ECS Transactions; Vol. 50, No. 8). https://doi.org/10.1149/05008.0161ecst