TY - GEN
T1 - Independent N and P process monitors for body bias based process corner correction
AU - Clark, Lawrence T.
AU - Kidd, David
AU - Agrawal, Vineet
AU - Leshner, Sam
AU - Krishnan, Gokul
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/11/4
Y1 - 2014/11/4
N2 - Process monitors that independently sense on-die PMOS and NMOS as-fabricated performance are presented. The monitors provide digital outputs, making them easily integrated blocks on SOC designs. We present two monitor approaches, one primarily analog and one primarily digital, applied to both logic circuits and SRAM, which may require different optimal body biases for best operation. The monitors correctly sense the die as-fabricated process corners on 55-nm test die, demonstrated on FF, FS, TT, SF SS corner skew lots. Experimentally measured performance and power correction is demonstrated for digital circuits, as well as parametric yield correction for SRAMs. Logic ring oscillators demonstrate 74% reduction in standard deviation for delay and leakage with monitor specified body biases. Similar improvement is demonstrated on embedded microprocessors. Finally, 55% and 72% reduction in SRAM read current variability and leakage, respectively, is also shown.
AB - Process monitors that independently sense on-die PMOS and NMOS as-fabricated performance are presented. The monitors provide digital outputs, making them easily integrated blocks on SOC designs. We present two monitor approaches, one primarily analog and one primarily digital, applied to both logic circuits and SRAM, which may require different optimal body biases for best operation. The monitors correctly sense the die as-fabricated process corners on 55-nm test die, demonstrated on FF, FS, TT, SF SS corner skew lots. Experimentally measured performance and power correction is demonstrated for digital circuits, as well as parametric yield correction for SRAMs. Logic ring oscillators demonstrate 74% reduction in standard deviation for delay and leakage with monitor specified body biases. Similar improvement is demonstrated on embedded microprocessors. Finally, 55% and 72% reduction in SRAM read current variability and leakage, respectively, is also shown.
UR - http://www.scopus.com/inward/record.url?scp=84928139406&partnerID=8YFLogxK
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U2 - 10.1109/CICC.2014.6946092
DO - 10.1109/CICC.2014.6946092
M3 - Conference contribution
AN - SCOPUS:84928139406
T3 - Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
BT - Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
Y2 - 15 September 2014 through 17 September 2014
ER -