In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches

Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky, Umit Ogras

Research output: Chapter in Book/Report/Conference proceedingConference contribution

27 Scopus citations

Abstract

In chip design today and for a foreseeable future, on-chip communication is not only a performance bottleneck but also a substantial power consumer. This work focuses on employing dynamic voltage and frequency scaling (DVFS) policies for networks-on-chip (NoC) and shared, distributed last-level caches (LLC). In particular, we consider a practical system architecture where the distributed LLC and the NoC share a voltage/frequency domain which is separate from the core domain. This architecture enables controlling the relative speed between the cores and memory hierarchy without introducing synchronization delays within the NoC. DVFS for this architecture is more difficult than individual link/core-based DVFS since it involves spatially distributed monitoring and control. We propose an average memory access time (AMAT)-based monitoring technique and integrate it with DVFS based on PID control theory. Simulations on PARSEC benchmarks yield a 33% dynamic energy savings with a negligible impact on system performance.

Original languageEnglish (US)
Title of host publicationProceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012
Pages43-50
Number of pages8
DOIs
StatePublished - Jun 29 2012
Externally publishedYes
Event2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012 - Copenhagen, Denmark
Duration: May 9 2012May 11 2012

Publication series

NameProceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012

Other

Other2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012
CountryDenmark
CityCopenhagen
Period5/9/125/11/12

Keywords

  • Multicore
  • NoC
  • dynamic power
  • memory system

ASJC Scopus subject areas

  • Hardware and Architecture

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