@inproceedings{7e244388fed841429e96a2e2ef2d916f,
title = "In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches",
abstract = "In chip design today and for a foreseeable future, on-chip communication is not only a performance bottleneck but also a substantial power consumer. This work focuses on employing dynamic voltage and frequency scaling (DVFS) policies for networks-on-chip (NoC) and shared, distributed last-level caches (LLC). In particular, we consider a practical system architecture where the distributed LLC and the NoC share a voltage/frequency domain which is separate from the core domain. This architecture enables controlling the relative speed between the cores and memory hierarchy without introducing synchronization delays within the NoC. DVFS for this architecture is more difficult than individual link/core-based DVFS since it involves spatially distributed monitoring and control. We propose an average memory access time (AMAT)-based monitoring technique and integrate it with DVFS based on PID control theory. Simulations on PARSEC benchmarks yield a 33% dynamic energy savings with a negligible impact on system performance.",
keywords = "Multicore, NoC, dynamic power, memory system",
author = "Xi Chen and Zheng Xu and Hyungjun Kim and Paul Gratz and Jiang Hu and Michael Kishinevsky and Umit Ogras",
year = "2012",
month = jun,
day = "29",
doi = "10.1109/NOCS.2012.12",
language = "English (US)",
isbn = "9780769546773",
series = "Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012",
pages = "43--50",
booktitle = "Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012",
note = "2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012 ; Conference date: 09-05-2012 Through 11-05-2012",
}