Implicit pseudo boolean enumeration algorithms for input vector control

Kaviraj Chopra, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identify the minimum leakage set of input vectors (MLS). Applying a vector in the MLS is known as Input Vector Control (IVC), and has proven to be very useful in reducing gate oxide leakage and sub-threshold leakage in standby mode of operation. The approach presented here is based on Implicit Enumeration of integer-valued decision diagrams. Since the search space for minimum leakage vector increases exponentially with the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. To reduce the switching power dissipated when the inputs are driven to a given state (during entry into and exit from the standby state), we extend the MLS algorithm to compute a bounded leakage set (BLS). Given a bound of standby leakage, we present an algorithm for computing minimal switching cost partial input vectors such that the leakage of the circuit is always less than the upper bound.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages767-772
Number of pages6
StatePublished - 2004
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004

Other

OtherProceedings of the 41st Design Automation Conference
CountryUnited States
CitySan Diego, CA
Period6/7/046/11/04

Fingerprint

Combinatorial circuits
Networks (circuits)
Logic circuits
Leakage currents
Oxides
Costs

Keywords

  • Binary Decision Diagrams
  • CMOS
  • Leakage
  • Power
  • SAT
  • Symbolic Methods

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Chopra, K., & Vrudhula, S. (2004). Implicit pseudo boolean enumeration algorithms for input vector control. In Proceedings - Design Automation Conference (pp. 767-772)

Implicit pseudo boolean enumeration algorithms for input vector control. / Chopra, Kaviraj; Vrudhula, Sarma.

Proceedings - Design Automation Conference. 2004. p. 767-772.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chopra, K & Vrudhula, S 2004, Implicit pseudo boolean enumeration algorithms for input vector control. in Proceedings - Design Automation Conference. pp. 767-772, Proceedings of the 41st Design Automation Conference, San Diego, CA, United States, 6/7/04.
Chopra K, Vrudhula S. Implicit pseudo boolean enumeration algorithms for input vector control. In Proceedings - Design Automation Conference. 2004. p. 767-772
Chopra, Kaviraj ; Vrudhula, Sarma. / Implicit pseudo boolean enumeration algorithms for input vector control. Proceedings - Design Automation Conference. 2004. pp. 767-772
@inproceedings{640e1218ba924211a4367933c5d0ec39,
title = "Implicit pseudo boolean enumeration algorithms for input vector control",
abstract = "In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identify the minimum leakage set of input vectors (MLS). Applying a vector in the MLS is known as Input Vector Control (IVC), and has proven to be very useful in reducing gate oxide leakage and sub-threshold leakage in standby mode of operation. The approach presented here is based on Implicit Enumeration of integer-valued decision diagrams. Since the search space for minimum leakage vector increases exponentially with the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. To reduce the switching power dissipated when the inputs are driven to a given state (during entry into and exit from the standby state), we extend the MLS algorithm to compute a bounded leakage set (BLS). Given a bound of standby leakage, we present an algorithm for computing minimal switching cost partial input vectors such that the leakage of the circuit is always less than the upper bound.",
keywords = "Binary Decision Diagrams, CMOS, Leakage, Power, SAT, Symbolic Methods",
author = "Kaviraj Chopra and Sarma Vrudhula",
year = "2004",
language = "English (US)",
pages = "767--772",
booktitle = "Proceedings - Design Automation Conference",

}

TY - GEN

T1 - Implicit pseudo boolean enumeration algorithms for input vector control

AU - Chopra, Kaviraj

AU - Vrudhula, Sarma

PY - 2004

Y1 - 2004

N2 - In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identify the minimum leakage set of input vectors (MLS). Applying a vector in the MLS is known as Input Vector Control (IVC), and has proven to be very useful in reducing gate oxide leakage and sub-threshold leakage in standby mode of operation. The approach presented here is based on Implicit Enumeration of integer-valued decision diagrams. Since the search space for minimum leakage vector increases exponentially with the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. To reduce the switching power dissipated when the inputs are driven to a given state (during entry into and exit from the standby state), we extend the MLS algorithm to compute a bounded leakage set (BLS). Given a bound of standby leakage, we present an algorithm for computing minimal switching cost partial input vectors such that the leakage of the circuit is always less than the upper bound.

AB - In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identify the minimum leakage set of input vectors (MLS). Applying a vector in the MLS is known as Input Vector Control (IVC), and has proven to be very useful in reducing gate oxide leakage and sub-threshold leakage in standby mode of operation. The approach presented here is based on Implicit Enumeration of integer-valued decision diagrams. Since the search space for minimum leakage vector increases exponentially with the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. To reduce the switching power dissipated when the inputs are driven to a given state (during entry into and exit from the standby state), we extend the MLS algorithm to compute a bounded leakage set (BLS). Given a bound of standby leakage, we present an algorithm for computing minimal switching cost partial input vectors such that the leakage of the circuit is always less than the upper bound.

KW - Binary Decision Diagrams

KW - CMOS

KW - Leakage

KW - Power

KW - SAT

KW - Symbolic Methods

UR - http://www.scopus.com/inward/record.url?scp=4444296151&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4444296151&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:4444296151

SP - 767

EP - 772

BT - Proceedings - Design Automation Conference

ER -