Implicit pseudo boolean enumeration algorithms for input vector control

Kaviraj Chopra, Sarma B K Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identify the minimum leakage set of input vectors (MLS). Applying a vector in the MLS is known as Input Vector Control (IVC), and has proven to be very useful in reducing gate oxide leakage and sub-threshold leakage in standby mode of operation. The approach presented here is based on Implicit Enumeration of integer-valued decision diagrams. Since the search space for minimum leakage vector increases exponentially with the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. To reduce the switching power dissipated when the inputs are driven to a given state (during entry into and exit from the standby state), we extend the MLS algorithm to compute a bounded leakage set (BLS). Given a bound of standby leakage, we present an algorithm for computing minimal switching cost partial input vectors such that the leakage of the circuit is always less than the upper bound.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages767-772
Number of pages6
StatePublished - 2004
Externally publishedYes
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004

Other

OtherProceedings of the 41st Design Automation Conference
CountryUnited States
CitySan Diego, CA
Period6/7/046/11/04

Keywords

  • Binary Decision Diagrams
  • CMOS
  • Leakage
  • Power
  • SAT
  • Symbolic Methods

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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