Implementation of a radix 2n multiplier using high performance logic

Sule Ozev; A. Altinordu; G. Dundar

Implementation of a radix 2ⁿ multiplier using high performance logic

Sule Ozev, A. Altinordu, G. Dundar

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this study, a 16 × 16 bit radix 2ⁿ multiplier was implemented using high performance logic. The design was done in a bottom-up style, where the performance of each block in the corresponding hierarchy was optimized starting from the transistor level. The performance of the radix 2ⁿ multiplier was compared with some existing multipliers.

Original language	English (US)
Title of host publication	Proceedings of the Mediterranean Electrotechnical Conference - MELECON
Editors	M. De Sario, B. Maione, P. Pugliese, M. Savino
Place of Publication	Piscataway, NJ, United States
Publisher	IEEE
Pages	469-472
Number of pages	4
Volume	1
State	Published - 1996
Externally published	Yes
Event	Proceedings of the 1996 8th Mediterranean Electrotechnical Conference, MELECON'06. Part 3 (of 3) - Bari, Italy Duration: May 13 1996 → May 16 1996

Other

Other	Proceedings of the 1996 8th Mediterranean Electrotechnical Conference, MELECON'06. Part 3 (of 3)
City	Bari, Italy
Period	5/13/96 → 5/16/96

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Implementation of a radix 2ⁿ multiplier using high performance logic. / Ozev, Sule; Altinordu, A.; Dundar, G.
Proceedings of the Mediterranean Electrotechnical Conference - MELECON. ed. / M. De Sario; B. Maione; P. Pugliese; M. Savino. Vol. 1 Piscataway, NJ, United States: IEEE, 1996. p. 469-472.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ozev, S, Altinordu, A & Dundar, G 1996, Implementation of a radix 2ⁿ multiplier using high performance logic. in M De Sario, B Maione, P Pugliese & M Savino (eds), Proceedings of the Mediterranean Electrotechnical Conference - MELECON. vol. 1, IEEE, Piscataway, NJ, United States, pp. 469-472, Proceedings of the 1996 8th Mediterranean Electrotechnical Conference, MELECON'06. Part 3 (of 3), Bari, Italy, 5/13/96.

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Implementation of a radix 2ⁿ multiplier using high performance logic

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