Implementation of a radix 2n multiplier using high performance logic

Sule Ozev, A. Altinordu, G. Dundar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this study, a 16 × 16 bit radix 2n multiplier was implemented using high performance logic. The design was done in a bottom-up style, where the performance of each block in the corresponding hierarchy was optimized starting from the transistor level. The performance of the radix 2n multiplier was compared with some existing multipliers.

Original languageEnglish (US)
Title of host publicationProceedings of the Mediterranean Electrotechnical Conference - MELECON
EditorsM. De Sario, B. Maione, P. Pugliese, M. Savino
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages469-472
Number of pages4
Volume1
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 8th Mediterranean Electrotechnical Conference, MELECON'06. Part 3 (of 3) - Bari, Italy
Duration: May 13 1996May 16 1996

Other

OtherProceedings of the 1996 8th Mediterranean Electrotechnical Conference, MELECON'06. Part 3 (of 3)
CityBari, Italy
Period5/13/965/16/96

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Ozev, S., Altinordu, A., & Dundar, G. (1996). Implementation of a radix 2n multiplier using high performance logic. In M. De Sario, B. Maione, P. Pugliese, & M. Savino (Eds.), Proceedings of the Mediterranean Electrotechnical Conference - MELECON (Vol. 1, pp. 469-472). IEEE.