Impact of vertical RRAM device characteristics on 3D cross-point array design

Resistive switching random access memory (RRAM) is one of the most promising candidates for the next-generation non-volatile memory. To enable large capacity RRAM array, the 3D architecture is needed. In this work, the analyses of different device characteristics, including the RRAM ON/OFF-state resistance (R_on/R_off), I-V nonlinearity ratio and the interconnect material, are performed to find the optimal design point of the 3D RRAM array. The results show that insufficient current drivability of the vertical transistor causes a significant amount of voltage drop on the transistor. The write and read margin conflicts with each other. A high R _on is preferred over a high nonlinearity to improve the write/read margin. A RRAM cell with R_on=500kΩ and nonlinearity=5x can satisfy the specified programming and read sense criterion for a 128×128×16 array, Moreover, the energy consumption (<nJ/bit) of the write operation outperforms that in NAND FLASH. Finally, a feature size (F) of 30nm and 60nm with equal array densities are compared, which suggests that the downscaling of feature size might not be as crucial as believed and the design constraint can be relaxed as a result.