Impact of temporal transistor variations on circuit reliability

Runsheng Wang, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

With the ever-increasing importance of temporal transistor variations during circuit run time and aging, this paper focuses on impacts of the two major temporal effects: the Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), illustrating their scaling trend, challenges, and potential solutions for future design robustness.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2453-2456
Number of pages4
Volume2015-July
ISBN (Print)9781479983919
DOIs
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period5/24/155/27/15

Keywords

  • bias temperature instability (BTI)
  • circuit reliability
  • random telegraph noise (RTN)
  • temporal variation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Wang, R., & Cao, Y. (2015). Impact of temporal transistor variations on circuit reliability. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2015-July, pp. 2453-2456). [7169181] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169181