TY - GEN
T1 - Impact of temporal transistor variations on circuit reliability
AU - Wang, Runsheng
AU - Cao, Yu
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/7/27
Y1 - 2015/7/27
N2 - With the ever-increasing importance of temporal transistor variations during circuit run time and aging, this paper focuses on impacts of the two major temporal effects: the Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), illustrating their scaling trend, challenges, and potential solutions for future design robustness.
AB - With the ever-increasing importance of temporal transistor variations during circuit run time and aging, this paper focuses on impacts of the two major temporal effects: the Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), illustrating their scaling trend, challenges, and potential solutions for future design robustness.
KW - bias temperature instability (BTI)
KW - circuit reliability
KW - random telegraph noise (RTN)
KW - temporal variation
UR - http://www.scopus.com/inward/record.url?scp=84946196830&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84946196830&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2015.7169181
DO - 10.1109/ISCAS.2015.7169181
M3 - Conference contribution
AN - SCOPUS:84946196830
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2453
EP - 2456
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -