Impact of stochastic mismatch on FinFETs SRAM cell induced by process variation

3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs SRAM cell induced by process variation including fin-thickness and gate length variation as well as fin line edge roughness (LER). In this work, 20nm FinFETs SRAM's sensitivity of read and write static noise margin (SNM) to process variation is evaluated. The worst cases of read and write SNM under the influence of process variation are summarized. The results show that FinFETs SRAM's stability is most sensitive to the access transistor's fin-thickness variation. Under the worst cases, increasing the pull-down transistor's fin-number may improve read SNM. The fin LER can cause aggressive fluctuations of the butterfly-curves and impose a big challenge on robust FinFETs SRAM design. Adopting 8T cell instead of 6T cell can alleviate the fin LER effect on read stability.