Impact of sampling clock phase noise on ΣΔ frequency discriminators

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Σ Δ frequency discriminators (SigmaDeltaFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a Σ ΔFD's spurious-free dynamic range (SFDR) is derived. It is shown that for Σ ΔFDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used Σ ΔFDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB.

Original languageEnglish (US)
Pages (from-to)949-953
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume54
Issue number11
DOIs
StatePublished - 2007

Fingerprint

Discriminators
Phase noise
Clocks
Sampling
Frequency synthesizers
Phase locked loops
Decoding
Calibration
Networks (circuits)
Communication

Keywords

  • ΣΔ modulators
  • Clock Jitter
  • Frequency discriminators

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Impact of sampling clock phase noise on ΣΔ frequency discriminators. / Kwon, Jiuk; Bakkaloglu, Bertan.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 54, No. 11, 2007, p. 949-953.

Research output: Contribution to journalArticle

@article{a3ebeebd88f2496fb568c34cb37eb6c1,
title = "Impact of sampling clock phase noise on ΣΔ frequency discriminators",
abstract = "Σ Δ frequency discriminators (SigmaDeltaFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a Σ ΔFD's spurious-free dynamic range (SFDR) is derived. It is shown that for Σ ΔFDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used Σ ΔFDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB.",
keywords = "ΣΔ modulators, Clock Jitter, Frequency discriminators",
author = "Jiuk Kwon and Bertan Bakkaloglu",
year = "2007",
doi = "10.1109/TCSII.2007.903783",
language = "English (US)",
volume = "54",
pages = "949--953",
journal = "IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing",
issn = "1549-7747",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",

}

TY - JOUR

T1 - Impact of sampling clock phase noise on ΣΔ frequency discriminators

AU - Kwon, Jiuk

AU - Bakkaloglu, Bertan

PY - 2007

Y1 - 2007

N2 - Σ Δ frequency discriminators (SigmaDeltaFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a Σ ΔFD's spurious-free dynamic range (SFDR) is derived. It is shown that for Σ ΔFDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used Σ ΔFDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB.

AB - Σ Δ frequency discriminators (SigmaDeltaFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a Σ ΔFD's spurious-free dynamic range (SFDR) is derived. It is shown that for Σ ΔFDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used Σ ΔFDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB.

KW - ΣΔ modulators

KW - Clock Jitter

KW - Frequency discriminators

UR - http://www.scopus.com/inward/record.url?scp=64749084911&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=64749084911&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2007.903783

DO - 10.1109/TCSII.2007.903783

M3 - Article

VL - 54

SP - 949

EP - 953

JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

SN - 1549-7747

IS - 11

ER -