Impact of sampling clock phase noise on ΣΔ frequency discriminators

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

Σ Δ frequency discriminators (SigmaDeltaFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a Σ ΔFD's spurious-free dynamic range (SFDR) is derived. It is shown that for Σ ΔFDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used Σ ΔFDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB.

Original languageEnglish (US)
Pages (from-to)949-953
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume54
Issue number11
DOIs
StatePublished - Dec 1 2007

Keywords

  • Clock Jitter
  • Frequency discriminators
  • ΣΔ modulators

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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