Impact of line-edge roughness on double-gate Schottky-barrier field-effect transistors

Shimeng Yu, Yuning Zhao, Lang Zeng, Gang Du, Jinfeng Kang, Ruqi Han, Xiaoyan Liu

Research output: Contribution to journalArticle

19 Scopus citations

Abstract

The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high-Vgs region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.

Original languageEnglish (US)
Pages (from-to)1211-1219
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume56
Issue number6
DOIs
StatePublished - May 18 2009

Keywords

  • FinFETs
  • Line-edge roughness (LER)
  • Parameter fluctuations
  • Process variations
  • SRAM stability
  • Schottky-barrier field-effect transistors (SBFETs)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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