Impact of channel length and gate width of a n-MOSFET device on the threshold voltage and its fluctuations in presence of random channel dopants and random interface trap: A 3D ensemble Monte Carlo study

Previously we have reported the correlation in the threshold voltage fluctuations caused by (1) the presence of random number and random distribution of dopant ions in the channel region of a 45 nm n-MOSFET and, (2) single interface trap positioned at random from source to drain of the n-MOSFET. In past work we have also supplemented the numerical simulations by results obtained with the usage of existing analytical models [1-4]. From the knowledge of random telegraph noise (RTN) based device physics data pertaining to scaled devices, it can be speculated that, as the gate width and the channel length are increased, the fluctuations in threshold voltage variations tend to decrease to manageable levels aiding in reliable device performance for both analog and digital ICs with long-term operational characteristics. The Ensemble Monte Carlo (EMC) device simulation results presented in this paper for a 70 nm gate length and 90 nm gate width n-MOSFET device confirm the above findings.